B
DFT Lead Engineer
Accepting applicationsBITSILICA · Bengaluru, Karnataka, India
Full-Time Mid_senior ATPGBISTDFTSoC
Estimated market salary
₹44-79 LPA
This is a SiliconBoard market estimate, not an employer-posted salary.
Posted
19h ago
Category
Test
Experience
Mid_senior
Country
India
8 to 10+ yrs of experience in DFT architecture, scan Insertion, compression at core level and SoC level.
Experience in ATPG pattern generation, coverage analysis
Experience with timing and no-timing simulations
Experience in Memory-BIST
Have understanding of SSN architecture, clock architecture, OCC
Show more Show less
Experience in ATPG pattern generation, coverage analysis
Experience with timing and no-timing simulations
Experience in Memory-BIST
Have understanding of SSN architecture, clock architecture, OCC
Show more Show less