MT
DFT Expert (15+ years)
Accepting applicationsMulya Technologies · Kochi, Kerala, India
Full-Time Principal ATEATPGBoundary SCANCadenceDFT
Posted
22h ago
Category
Test
Experience
Principal
Country
India
DFT Expert
Among. The top 4 IT companies, in India ranked by market capitalization and revenue
Bangalore / Hyderabad / Kochi
Reference JD:
1. Ability to define Test plan and Test strategy at partition level and full chip level
2. Experience in Scan chain insertion, chain balancing
3. Experience in Boundary SCAN (BSCAN)
4. Test structure insertion at RTL level and/or at netlist level
5. Test pattern generation – stuck at and transition faults (ATPG)
6. Validation of Test pattens by doing pattern simulations including GLS
7. Coverage analysis, ability to detect coverage holes at early stage and ensure coverage targets are met
8. Insertion of MBIST and carrying out MBIST simulations
9. Ability to provide support during Silicon bring up on ATE
10. Good verbal and written communication skills
11. Should be able to manage a team of DFT engineers in the experience range of 3-12 years to ensure their deliveries meet requirements
12. Must be familiar with industry standard tools and flows (Siemens/Cadence/Synopsys). Good handle on scripting.
13. Experience with SSN would be added advantage
14. Ideally a 15+ years experienced DFT expert who has performed the above duties for one or two projects in the recent past
Skills
DFT
HPC
"low power design"
architecture
modus
tessent
testmax
atpg
mbist
lbist
GLS
ATE
tetramax
DFTmax
DFT compiler
DFT advisor
Fastscan
Contact
Uday
muday_bhaskar@yahoo.com
Mulya Technologies
"Mining the Knowledge Community"
Show more Show less
Among. The top 4 IT companies, in India ranked by market capitalization and revenue
Bangalore / Hyderabad / Kochi
Reference JD:
1. Ability to define Test plan and Test strategy at partition level and full chip level
2. Experience in Scan chain insertion, chain balancing
3. Experience in Boundary SCAN (BSCAN)
4. Test structure insertion at RTL level and/or at netlist level
5. Test pattern generation – stuck at and transition faults (ATPG)
6. Validation of Test pattens by doing pattern simulations including GLS
7. Coverage analysis, ability to detect coverage holes at early stage and ensure coverage targets are met
8. Insertion of MBIST and carrying out MBIST simulations
9. Ability to provide support during Silicon bring up on ATE
10. Good verbal and written communication skills
11. Should be able to manage a team of DFT engineers in the experience range of 3-12 years to ensure their deliveries meet requirements
12. Must be familiar with industry standard tools and flows (Siemens/Cadence/Synopsys). Good handle on scripting.
13. Experience with SSN would be added advantage
14. Ideally a 15+ years experienced DFT expert who has performed the above duties for one or two projects in the recent past
Skills
DFT
HPC
"low power design"
architecture
modus
tessent
testmax
atpg
mbist
lbist
GLS
ATE
tetramax
DFTmax
DFT compiler
DFT advisor
Fastscan
Contact
Uday
muday_bhaskar@yahoo.com
Mulya Technologies
"Mining the Knowledge Community"
Show more Show less