WA
DFT engineers
Accepting applicationsWeekday AI (YC W21) · Hyderabad, Telangana, India
Full-Time Mid_senior ASICATPGDFTRTLSoC
Posted
19h ago
Category
Test
Experience
Mid_senior
Country
India
This role is for one of Weekday's clients
Min Experience: 4+ years
Location: Hyderabad, Bengaluru, Karnataka, India
JobType: full-time
We are looking for a skilled and experienced DFT Engineer with 4-12 years of experience in semiconductor design and test methodologies. The ideal candidate will have strong hands-on expertise in ATPG and Scan Insertion, with a solid understanding of DFT architecture, testability requirements, and silicon validation. Experience with MBIST will be an added advantage.
You will work closely with RTL design, physical design, verification, and product engineering teams to develop and implement robust DFT solutions for complex SoCs and ASICs. The role involves driving DFT implementation from architecture and insertion through ATPG generation, pattern validation, coverage analysis, and production readiness.
Requirements
Key Responsibilities
Develop and implement DFT architectures and methodologies for ASIC/SoC designs
Perform scan insertion across hierarchical and full-chip designs while ensuring design integrity and testability
Develop, configure, and debug ATPG environments for stuck-at, transition, and other applicable fault models
Generate, validate, and optimize ATPG patterns to achieve high fault coverage and efficient test application
Analyze ATPG results, identify coverage gaps, and implement corrective measures to improve test coverage
Work on scan chain configuration, stitching, balancing, and verification
Debug DFT-related issues across RTL, gate-level netlists, and post-synthesis/post-layout stages
Collaborate with RTL, synthesis, physical design, STA, verification, and validation teams to resolve DFT implementation challenges
Review DFT constraints and ensure compatibility with synthesis and physical implementation flows
Perform DFT rule checks, identify violations, and support their closure
Analyze test coverage, pattern quality, test time, and compression requirements
Support gate-level simulations and debug test pattern failures
Contribute to improving DFT methodologies, automation scripts, and overall test efficiency
Support silicon bring-up and post-silicon debug when required
Must-Have Skills
ATPG
Strong hands-on experience with ATPG generation and pattern development
Good understanding of stuck-at, transition, and other fault models
Experience with ATPG coverage analysis, pattern debugging, and coverage improvement
Understanding of test compression and scan-based testing methodologies
Scan Insertion
Strong experience in scan insertion and scan chain implementation
Knowledge of scan architecture, scan stitching, chain balancing, and DFT rule checks
Experience debugging scan-related issues at RTL and gate level
Understanding of DFT constraints and their interaction with synthesis and physical design flows
Good-to-Have Skills
MBIST
Exposure to Memory Built-In Self-Test (MBIST) architecture and implementation
Understanding of memory test algorithms, controllers, and MBIST pattern generation
Experience integrating or validating MBIST solutions in SoC/ASIC designs
Preferred Qualifications
Bachelor's or Master's degree in Electronics, Electrical Engineering, VLSI, Microelectronics, or a related field
4-12 years of relevant experience in DFT/ASIC/SoC development
Strong analytical and debugging skills with the ability to work across multiple design teams
Experience with industry-standard DFT/ATPG tools and semiconductor design flows is highly desirable
Good communication and collaboration skills, with the ability to work effectively in cross-functional engineering teams
Show more Show less
Min Experience: 4+ years
Location: Hyderabad, Bengaluru, Karnataka, India
JobType: full-time
We are looking for a skilled and experienced DFT Engineer with 4-12 years of experience in semiconductor design and test methodologies. The ideal candidate will have strong hands-on expertise in ATPG and Scan Insertion, with a solid understanding of DFT architecture, testability requirements, and silicon validation. Experience with MBIST will be an added advantage.
You will work closely with RTL design, physical design, verification, and product engineering teams to develop and implement robust DFT solutions for complex SoCs and ASICs. The role involves driving DFT implementation from architecture and insertion through ATPG generation, pattern validation, coverage analysis, and production readiness.
Requirements
Key Responsibilities
Develop and implement DFT architectures and methodologies for ASIC/SoC designs
Perform scan insertion across hierarchical and full-chip designs while ensuring design integrity and testability
Develop, configure, and debug ATPG environments for stuck-at, transition, and other applicable fault models
Generate, validate, and optimize ATPG patterns to achieve high fault coverage and efficient test application
Analyze ATPG results, identify coverage gaps, and implement corrective measures to improve test coverage
Work on scan chain configuration, stitching, balancing, and verification
Debug DFT-related issues across RTL, gate-level netlists, and post-synthesis/post-layout stages
Collaborate with RTL, synthesis, physical design, STA, verification, and validation teams to resolve DFT implementation challenges
Review DFT constraints and ensure compatibility with synthesis and physical implementation flows
Perform DFT rule checks, identify violations, and support their closure
Analyze test coverage, pattern quality, test time, and compression requirements
Support gate-level simulations and debug test pattern failures
Contribute to improving DFT methodologies, automation scripts, and overall test efficiency
Support silicon bring-up and post-silicon debug when required
Must-Have Skills
ATPG
Strong hands-on experience with ATPG generation and pattern development
Good understanding of stuck-at, transition, and other fault models
Experience with ATPG coverage analysis, pattern debugging, and coverage improvement
Understanding of test compression and scan-based testing methodologies
Scan Insertion
Strong experience in scan insertion and scan chain implementation
Knowledge of scan architecture, scan stitching, chain balancing, and DFT rule checks
Experience debugging scan-related issues at RTL and gate level
Understanding of DFT constraints and their interaction with synthesis and physical design flows
Good-to-Have Skills
MBIST
Exposure to Memory Built-In Self-Test (MBIST) architecture and implementation
Understanding of memory test algorithms, controllers, and MBIST pattern generation
Experience integrating or validating MBIST solutions in SoC/ASIC designs
Preferred Qualifications
Bachelor's or Master's degree in Electronics, Electrical Engineering, VLSI, Microelectronics, or a related field
4-12 years of relevant experience in DFT/ASIC/SoC development
Strong analytical and debugging skills with the ability to work across multiple design teams
Experience with industry-standard DFT/ATPG tools and semiconductor design flows is highly desirable
Good communication and collaboration skills, with the ability to work effectively in cross-functional engineering teams
Show more Show less