TM
DFT Engineer (Scan Insertion & ATPG)
Accepting applicationsTech Mahindra · Bengaluru, Karnataka, India
Full-Time Mid_senior ASICATPGAnalogCadenceDFT
Posted
2d ago
Category
Test
Experience
Mid_senior
Country
India
Brief About Tech Mahindra – Silicon Engineering
Tech Mahindra Silicon Engineering is a key part of Tech Mahindra’s semiconductor and engineering services portfolio, delivering end-to-end solutions across the silicon lifecycle for global semiconductor, automotive, consumer, networking, and industrial clients. The practice focuses on VLSI, Embedded Systems, SoC Design, and Platform Engineering, supporting customers from architecture and RTL design through implementation, verification, validation, and post-silicon support.
The Silicon Engineering unit works across IP, Sub-System, and SoC-level development, offering deep expertise in areas such as Physical Design, RTL Design, Design Verification, DFT, Analog/Mixed-Signal Design, Post-Silicon Validation, Embedded Software, and System Engineering. Teams leverage industry-leading EDA tools and advanced implementation methodologies to deliver high-performance, low-power, and manufacturable silicon solutions.
Backed by Tech Mahindra’s global engineering DNA, the Silicon Engineering practice collaborates with leading semiconductor and technology companies worldwide, serving as an extended engineering arm to accelerate silicon development programs, optimize design quality, and enable faster time-to-market for next-generation SoCs and products.
About the Role – In this exciting role, you will be responsible for implementing and validating Design-for-Test (DFT) methodologies for complex ASIC and SoC designs. You will work closely with Design, Verification, Physical Design, and Test Engineering teams to ensure high-quality manufacturing test solutions through Scan Insertion, ATPG, Pattern Simulation, and DFT signoff activities. The role offers exposure to advanced DFT methodologies, debugging, and automation within a highly collaborative semiconductor environment.
Key Responsibilities
Execute complete Scan Insertion and DFT implementation for complex ASIC and SoC designs.
Generate and optimize ATPG patterns to achieve target fault coverage and test quality goals.
Perform Pattern Simulation and analyze simulation results to validate generated test patterns.
Debug and resolve DFT DRC (Design Rule Check) violations during implementation and signoff stages.
Analyze fault coverage reports and identify opportunities to improve test efficiency and coverage.
Collaborate with RTL, Physical Design, STA, and Verification teams to ensure DFT readiness and smooth design convergence.
Support manufacturing test requirements, silicon bring-up, and failure analysis activities when required.
Develop and maintain automation scripts using Perl for DFT flow execution, report generation, and debug activities.
Perform DFT quality checks including Scan Chain Verification, DRC analysis, ATPG validation, and pattern certification.
Participate in technical reviews, customer discussions, and process improvement initiatives.
Work closely with global engineering teams to meet project schedules, quality targets, and tape-out milestones.
Contribute to DFT methodology enhancement and best-practice development across projects.
Qualifications – BE/BTech/ME/MTech degree in Electronics, Electrical, Telecommunications, Microelectronics, VLSI Design, or related engineering disciplines.
Required Skills
Strong experience in DFT implementation with hands-on expertise in Scan Insertion and ATPG.
Hands-on experience in Pattern Generation and Pattern Simulation for ASIC/SoC designs.
Experience in identifying and fixing DFT DRC violations and design rule issues.
Strong understanding of fault models including Stuck-at Faults, Transition Faults, and Delay Faults.
Hands-on experience with industry-standard DFT tools such as Siemens Tessent, Synopsys TestMAX/DFT Compiler, or Cadence Modus.
Good understanding of digital design, ASIC/SoC development flow, and test methodologies.
Basic knowledge of Perl scripting for automation and debug activities.
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Tech Mahindra Silicon Engineering is a key part of Tech Mahindra’s semiconductor and engineering services portfolio, delivering end-to-end solutions across the silicon lifecycle for global semiconductor, automotive, consumer, networking, and industrial clients. The practice focuses on VLSI, Embedded Systems, SoC Design, and Platform Engineering, supporting customers from architecture and RTL design through implementation, verification, validation, and post-silicon support.
The Silicon Engineering unit works across IP, Sub-System, and SoC-level development, offering deep expertise in areas such as Physical Design, RTL Design, Design Verification, DFT, Analog/Mixed-Signal Design, Post-Silicon Validation, Embedded Software, and System Engineering. Teams leverage industry-leading EDA tools and advanced implementation methodologies to deliver high-performance, low-power, and manufacturable silicon solutions.
Backed by Tech Mahindra’s global engineering DNA, the Silicon Engineering practice collaborates with leading semiconductor and technology companies worldwide, serving as an extended engineering arm to accelerate silicon development programs, optimize design quality, and enable faster time-to-market for next-generation SoCs and products.
About the Role – In this exciting role, you will be responsible for implementing and validating Design-for-Test (DFT) methodologies for complex ASIC and SoC designs. You will work closely with Design, Verification, Physical Design, and Test Engineering teams to ensure high-quality manufacturing test solutions through Scan Insertion, ATPG, Pattern Simulation, and DFT signoff activities. The role offers exposure to advanced DFT methodologies, debugging, and automation within a highly collaborative semiconductor environment.
Key Responsibilities
Execute complete Scan Insertion and DFT implementation for complex ASIC and SoC designs.
Generate and optimize ATPG patterns to achieve target fault coverage and test quality goals.
Perform Pattern Simulation and analyze simulation results to validate generated test patterns.
Debug and resolve DFT DRC (Design Rule Check) violations during implementation and signoff stages.
Analyze fault coverage reports and identify opportunities to improve test efficiency and coverage.
Collaborate with RTL, Physical Design, STA, and Verification teams to ensure DFT readiness and smooth design convergence.
Support manufacturing test requirements, silicon bring-up, and failure analysis activities when required.
Develop and maintain automation scripts using Perl for DFT flow execution, report generation, and debug activities.
Perform DFT quality checks including Scan Chain Verification, DRC analysis, ATPG validation, and pattern certification.
Participate in technical reviews, customer discussions, and process improvement initiatives.
Work closely with global engineering teams to meet project schedules, quality targets, and tape-out milestones.
Contribute to DFT methodology enhancement and best-practice development across projects.
Qualifications – BE/BTech/ME/MTech degree in Electronics, Electrical, Telecommunications, Microelectronics, VLSI Design, or related engineering disciplines.
Required Skills
Strong experience in DFT implementation with hands-on expertise in Scan Insertion and ATPG.
Hands-on experience in Pattern Generation and Pattern Simulation for ASIC/SoC designs.
Experience in identifying and fixing DFT DRC violations and design rule issues.
Strong understanding of fault models including Stuck-at Faults, Transition Faults, and Delay Faults.
Hands-on experience with industry-standard DFT tools such as Siemens Tessent, Synopsys TestMAX/DFT Compiler, or Cadence Modus.
Good understanding of digital design, ASIC/SoC development flow, and test methodologies.
Basic knowledge of Perl scripting for automation and debug activities.
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