DFT Engineer in Hyderabad/Bangalore

Skill: DFT - DFT (Design for Test) is a specialized domain in the semiconductor/VLSI industry that ensures integrated circuits (ASICs/SoCs) are testable during manufacturing. DFT engineers design and implement test structures such as Scan, ATPG, MBIST, LBIST, and JTAG to improve chip quality, fault coverage, and manufacturing yield.

Key skills to target:
End-to-end DFT implementation
Scan insertion & compression, ATPG
MBIST, LBIST, JTAG/Boundary Scan
DFT signoff, fault coverage, debugging
RTL, SoC design flow, STA
Tools: Siemens Tessent, Synopsys TestMAX, Cadence Modus
Scripting: TCL, Python, Perl

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A DFT Staff Engineer is responsible for designing, implementing, and signing off Design-for-Test (DFT)architecture for complexSoCs/IPs. The roleensures that semiconductor designs are testable, high-quality, and manufacturable, whilebalancing coverage, performance, power, and cost.
Key Responsibilities
DFT Architecture G Strategy
Define and implement DFT architecture at block/IP or SoC level
Specify test methodologies (scan,MBIST, boundary scan,compression)
Ensure testability built early into RTL design flow
Balance trade-offs between coverage, area, power, and test time
DFT Implementation Perform:
Scan insertion and stitching
ATPG pattern generation and simulation
MBIST / LBIST / boundary scan integration
Develop and validate DFT timing constraints (STA)
Execute DFT flows at RTL and gate level
Test Coverage G Ǫuality
Analyze and improve fault coverage
Debug scan/ATPG issues and resolve coverageholes
Optimize:
Pattern count
Test cost
Test time
Verification G Signoff
Run DFT verification and DRC checks
Ensure clean DFT signoff (coverage, timing, power impact)
Validate patterns using simulation and test tools
Support DFT integration guidelines at SoC level
Cross-Functional Collaboration Work with:
RTL design
Physical design (PD)
Verification

Test engineering / ATE
Drive issue resolution acrossteams
Ensure end-to-end execution of DFT flows
SiliconBring-up G Debug
Support post-silicon debug and yield improvement
Debug tester failures and improve manufacturing coverage
Assist customer or productteams during bring-up
Required Skills G Expertise Core Technical Skills Strong expertise in:
Scan (insertion, compression)
ATPG C fault models
MBIST / LBIST
JTAG / Boundary Scan (IEEE 1149.1)
Good understanding of:
RTL design C verification
STA and timing closure
SoC designflow
Tools
Synopsys / Cadence / Siemens tools (e.g., TestMAX, Tessent, Modus)
Simulation tools (VCS, etc.)
Scripting: TCL, Python, Perl
Ǫualifications
BSEE/MSEE (or equivalent)
Typically 7+ years of DFT / ASIC experience (Staff-level expectation)
Proven experience in end-to-end DFT implementation and debugging

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