WS
DFT Engineer
Accepting applicationsWayfinder Solutions Pvt ltd. · Bengaluru, Karnataka, India
Full-Time Entry ATPGCadenceDFTSoCSynopsys
Estimated market salary
₹8-14 LPA
This is a SiliconBoard market estimate, not an employer-posted salary.
Posted
21h ago
Category
Test
Experience
Entry
Country
India
DFT Engineer (Senior/Manager)
Domain: Hardware / Chip Design & Embedded Software
Experience: 3 – 15 Years
Job Type: Full Time
Location: India – Bangalore
About the Company
Our client is a trusted semiconductor company that has satisfied major clients in the semiconductor market. Established in 2017 and headquartered in India, the organization is committed to attracting and developing a diverse workforce of DFT professionals who share the common value of collaboration.
We believe in teaming together with our clients to see beyond the surface of changes and problems organizations face in this fast-changing world, to discover opportunities others might miss, and to face the future with greater confidence.
Role Overview
We are hiring experienced candidates in the DFT segment for the position of DFT Engineer based in Bangalore, India.
Experience Required: 3 – 15 Years
Key Responsibilities & Requirements
The candidate is expected to have a clear understanding of BSCAN, MBIST, SCAN, ATPG and Simulation concepts.
Should have experience in at least one of the following:
MBIST insertion
Scan Insertion
ATPG pattern generation and simulations
MBIST and BSCAN simulations using industry standard tools of Cadence / Siemens Tessent / Synopsys.
Good to have worked on zero delay as well as SDF Timing Simulations.
Should have good debugging skills using GUI mode of industry standard simulators like VCS, NCSim or Xcelium.
Good to have worked on fault models like stuck-at, Transition Delay Faults (TDF), IDDQ and should have experience in scan test coverage improvement techniques.
Candidate should have worked in SoC level DFT with experience in:
OCC/OPCG insertion
EDT/Compression logic insertion
Clock module handling for scan purposes
Post-silicon bring-up and/or production activities with exposure to Tester debug using shmoo plots and graphs.
The candidate should have experience of providing test mode timing constraints to STA and PD teams.
Soft Skills:
Good communication skills and debugging skills are a must-have qualities for this role as it involves cross-functional teams and customer teams communications along with internal DFT team leading and mentoring of DFT Engineers.
Additional Details
Work Mode: Should be okay for working from office, but it could be hybrid or remote depending on projects.
Job Stability: Minimum 2 years in an organisation.
Notice Period: Immediate to 60 days.
Interview Process: 2 to 3 rounds of virtual interviews + HR.
Working Hours: Regular work hours.
Show more Show less
Domain: Hardware / Chip Design & Embedded Software
Experience: 3 – 15 Years
Job Type: Full Time
Location: India – Bangalore
About the Company
Our client is a trusted semiconductor company that has satisfied major clients in the semiconductor market. Established in 2017 and headquartered in India, the organization is committed to attracting and developing a diverse workforce of DFT professionals who share the common value of collaboration.
We believe in teaming together with our clients to see beyond the surface of changes and problems organizations face in this fast-changing world, to discover opportunities others might miss, and to face the future with greater confidence.
Role Overview
We are hiring experienced candidates in the DFT segment for the position of DFT Engineer based in Bangalore, India.
Experience Required: 3 – 15 Years
Key Responsibilities & Requirements
The candidate is expected to have a clear understanding of BSCAN, MBIST, SCAN, ATPG and Simulation concepts.
Should have experience in at least one of the following:
MBIST insertion
Scan Insertion
ATPG pattern generation and simulations
MBIST and BSCAN simulations using industry standard tools of Cadence / Siemens Tessent / Synopsys.
Good to have worked on zero delay as well as SDF Timing Simulations.
Should have good debugging skills using GUI mode of industry standard simulators like VCS, NCSim or Xcelium.
Good to have worked on fault models like stuck-at, Transition Delay Faults (TDF), IDDQ and should have experience in scan test coverage improvement techniques.
Candidate should have worked in SoC level DFT with experience in:
OCC/OPCG insertion
EDT/Compression logic insertion
Clock module handling for scan purposes
Post-silicon bring-up and/or production activities with exposure to Tester debug using shmoo plots and graphs.
The candidate should have experience of providing test mode timing constraints to STA and PD teams.
Soft Skills:
Good communication skills and debugging skills are a must-have qualities for this role as it involves cross-functional teams and customer teams communications along with internal DFT team leading and mentoring of DFT Engineers.
Additional Details
Work Mode: Should be okay for working from office, but it could be hybrid or remote depending on projects.
Job Stability: Minimum 2 years in an organisation.
Notice Period: Immediate to 60 days.
Interview Process: 2 to 3 rounds of virtual interviews + HR.
Working Hours: Regular work hours.
Show more Show less
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