VS
DFT Engineer
Accepting applicationsVGAI Solutions · Santa Clara, CA
Contract Mid_senior ASICATPGDFTMentorSoC
Posted
1d ago
Category
Test
Experience
Mid_senior
Country
United States
We are seeking a Senior DFT Engineer with 8–12 years of relevant experience in DFT Scan Insertion and ATPG Validation. The ideal candidate will have strong hands-on experience with industry-standard DFT methodologies, scan architecture, ATPG flows, and DFT implementation.
The candidate should have practical experience working with Mentor Tessent (Siemens) and Synopsys DFT Compiler, along with a strong understanding of scan insertion, ATPG generation, validation, debugging, and DFT-related issues.
Senior DFT Engineer – Scan Insertion & ATPG Validation
Duration: 12 Months
Location: Santa Clara, CA
Experience: 8–12 Years
Key Responsibilities
Perform DFT Scan Insertion and support scan architecture implementation.
Develop, execute, and validate ATPG flows and test patterns.
Analyze and debug ATPG and DFT-related issues.
Work with design and verification teams to resolve scan and testability issues.
Support DFT implementation, validation, and sign-off activities.
Apply industry-standard DFT methodologies throughout the ASIC/SoC design flow.
Required Qualifications
8–12 years of hands-on DFT engineering experience.
Strong experience in DFT Scan Insertion.
Hands-on experience with ATPG Validation.
Strong understanding of DFT methodologies, scan architecture, and ATPG flows.
Experience in ASIC/SoC semiconductor design environments.
Strong debugging and problem-solving skills.
Required Tools
Mentor Tessent / Siemens Tessent
Synopsys DFT Compiler
Show more Show less
The candidate should have practical experience working with Mentor Tessent (Siemens) and Synopsys DFT Compiler, along with a strong understanding of scan insertion, ATPG generation, validation, debugging, and DFT-related issues.
Senior DFT Engineer – Scan Insertion & ATPG Validation
Duration: 12 Months
Location: Santa Clara, CA
Experience: 8–12 Years
Key Responsibilities
Perform DFT Scan Insertion and support scan architecture implementation.
Develop, execute, and validate ATPG flows and test patterns.
Analyze and debug ATPG and DFT-related issues.
Work with design and verification teams to resolve scan and testability issues.
Support DFT implementation, validation, and sign-off activities.
Apply industry-standard DFT methodologies throughout the ASIC/SoC design flow.
Required Qualifications
8–12 years of hands-on DFT engineering experience.
Strong experience in DFT Scan Insertion.
Hands-on experience with ATPG Validation.
Strong understanding of DFT methodologies, scan architecture, and ATPG flows.
Experience in ASIC/SoC semiconductor design environments.
Strong debugging and problem-solving skills.
Required Tools
Mentor Tessent / Siemens Tessent
Synopsys DFT Compiler
Show more Show less