VI

DFT Engineer

Accepting applications

VARITE INC · Santa Clara, CA

Full-Time Mid_senior ATPGBoundary ScanBoundary scanDFTJTAG
Posted
4d ago
Category
Test
Experience
Mid_senior
Country
United States
VARITE is looking for qualified DFT Engineers in Santa, CA/Austin, TX/Phoenix, AZ/Boston, MA/Seattle, WA/Portland, OR .

WHAT THE CLIENT DOES?
An Multinational technology company that provides engineering research and development (ER&D) services. The company's business interests include automotive engineering, embedded systems and semiconductor engineering, industrial internet of things, manufacturing plant engineering, and medical engineering.

WHAT WE DO?
Established in the Year 2000, VARITE is an award-winning minority business enterprise providing global consulting & staffing services to Fortune 1000 companies and government agencies. With 850+ global consultants, VARITE is committed to delivering excellence to its customers by leveraging its global experience and expertise in providing comprehensive scientific, engineering, technical, and non-technical staff augmentation and talent acquisition services.

Job Title: DFT Engineers
Location: Santa, CA/Austin, TX/Phoenix, AZ/Boston, MA/Seattle, WA/Portland, OR
Contract Duration: Full-Time
Pay Rate Range: $180K/Annum to $200K/Annum
Open - C2C/W2

HERE’S WHAT YOU’LL DO
Job Summary:
We are seeking experienced DFT Engineers with strong expertise in Design-for-Test (DFT) and DFx verification to support advanced semiconductor programs. The role focuses on DFT implementation, integration, and verification of DFT features across complex SoCs.
Scan (including SSN architectures)
MBIST
Boundary Scan
JTAG
SCAN
MBIST
High-Speed IO interfaces

Key Responsibilities:
Repair architecture integration
Verification and validation
Develop and validate ICL and PDL descriptions
Ensure compliance with IJTAG standards
Test timing
Physical design (Place & Route)

Nature and Scope:
Scan insertion and debugging
MBIST architecture and verification
Boundary scan and JTAG protocols
Experience with IJTAG (1687), ICL, and PDL standards
Familiarity with high-speed IO test methodologies
Experience working with DFT tools (preferably Siemens/Tessent suite)
Good understanding of test timing and physical design impact on DFT

Must Haves:
Exposure to large SoC environments and advanced nodes
Experience in cross-functional debug and silicon bring-up
Prior experience with automation or scripting (Python/Perl)
5+ years of relevant DFT experience
ATPG experience good to have

Benefits:
We offer a comprehensive benefits package designed to support the health, well-being, and financial security of our employees and their families. Eligible employees may receive:
Health Insurance: Medical, dental, and vision coverage
Retirement Plans: Participation in a company-sponsored retirement savings plan.
Legal Service Plans: Offering access to attorneys for legal advice and representation.

If this opportunity interests you, please respond by clicking on EasyApply.

Know someone who would be perfect for this role? Refer to us and if they are hired, you could be eligible for our employee referral bonus! Help us grow our team with top talent from your network.
VARITE is committed to creating a diverse environment and is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, gender, gender identity or expression, sexual orientation, national origin, genetics, disability, age, or veteran status.


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