VI
DFT Engineer
Accepting applicationsValue Innovation Labs · Mountain View, CA
Contract Mid_senior ASICATEATPGDFTJTAG
Posted
2d ago
Category
Test
Experience
Mid_senior
Country
United States
🚨 Hiring: DFT Engineer
📍 Location: Mountain View, CA
🏢 Work Mode: Onsite
🛂 Visa: US Citizen / Green Card ONLY
💼 Experience: 6+ Years
We are looking for an experienced DFT Engineer with strong expertise in DFT architecture, implementation, ATPG, and SoC verification.
🔹 Key Responsibilities & Skills
• DFT Architecture, Implementation, ATPG & Verification
• DFT for SoCs
• ATE, MBIST, JTAG & System Level Test (SLT)
• DFT flow and IP integration
• Test Controllers, TAP & MBIST
• Interaction with Synthesis and Verification flows
• Industry-standard DFT EDA tools
• Synopsys Design Compiler / DFTMAX
• Siemens EDA Tessent / TestKompress
• Silicon process and advanced technology nodes
• High-speed and low-power design considerations
• Fault Models: Stuck-at, Transition, Cell-Aware, Path Delay, etc.
🎓 Education: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, related field, or equivalent practical experience.
📩 Interested candidates? DM me your updated resume.
#Hiring #DFT #DFTEngineer #Broadcom #ASIC #VLSI #Semiconductor #ATPG #MBIST #JTAG #SLT #Tessent #TestKompress #DFTMax #DesignCompiler #SoC #Silicon #MountainView #California #USJobs #USCitizen #GreenCard
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📍 Location: Mountain View, CA
🏢 Work Mode: Onsite
🛂 Visa: US Citizen / Green Card ONLY
💼 Experience: 6+ Years
We are looking for an experienced DFT Engineer with strong expertise in DFT architecture, implementation, ATPG, and SoC verification.
🔹 Key Responsibilities & Skills
• DFT Architecture, Implementation, ATPG & Verification
• DFT for SoCs
• ATE, MBIST, JTAG & System Level Test (SLT)
• DFT flow and IP integration
• Test Controllers, TAP & MBIST
• Interaction with Synthesis and Verification flows
• Industry-standard DFT EDA tools
• Synopsys Design Compiler / DFTMAX
• Siemens EDA Tessent / TestKompress
• Silicon process and advanced technology nodes
• High-speed and low-power design considerations
• Fault Models: Stuck-at, Transition, Cell-Aware, Path Delay, etc.
🎓 Education: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, related field, or equivalent practical experience.
📩 Interested candidates? DM me your updated resume.
#Hiring #DFT #DFTEngineer #Broadcom #ASIC #VLSI #Semiconductor #ATPG #MBIST #JTAG #SLT #Tessent #TestKompress #DFTMax #DesignCompiler #SoC #Silicon #MountainView #California #USJobs #USCitizen #GreenCard
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