T
DFT Engineer
Accepting applicationsTruechip · Hyderabad, Telangana, India
Full-Time Entry ATPGBoundary ScanCadenceDFTJTAG
Estimated market salary
₹7-13 LPA
This is a SiliconBoard market estimate, not an employer-posted salary.
Posted
21h ago
Category
Test
Experience
Entry
Country
India
DFT Engineer
Location: Bangalore, India
Experience: 2–8 Years
Employment Type: Full-time
About the Role
Truechip is looking for a highly motivated DFT Engineer to join our engineering team. The role involves working on Design-for-Test (DFT) architecture, implementation, verification, and debug for complex SoC and IP designs.
The ideal candidate should have strong fundamentals in digital design and hands-on experience with DFT methodologies, including scan insertion, ATPG, MBIST, JTAG, and test coverage analysis.
Key Responsibilities
Develop and implement DFT architectures for complex SoC/IP designs.
Perform scan insertion, scan stitching, and DFT rule checking.
Develop and analyze ATPG patterns and improve fault coverage.
Work on stuck-at, transition, and other production fault models.
Implement and verify MBIST/LBIST solutions.
Work on JTAG / IEEE 1149.1 Boundary Scan and related test architectures.
Perform DFT verification, simulation, pattern validation, and debug.
Analyze DFT-related violations and resolve implementation issues.
Collaborate with RTL, Design Verification, Physical Design, and SoC teams.
Debug test coverage, timing, scan-chain, and pattern-related issues.
Support DFT sign-off and contribute to improving test quality and coverage.
Participate in customer engagements and provide technical support when required.
Required Skills
Strong understanding of Digital Design and DFT concepts.
Hands-on experience with Scan, ATPG, MBIST, LBIST, and JTAG.
Good knowledge of fault models and fault coverage analysis.
Experience with DFT/ATPG tools such as Synopsys TestMAX/TetraMAX, Siemens Tessent, Cadence Modus, or equivalent.
Understanding of scan compression, EDT, test modes, and test clocks.
Good knowledge of Verilog/SystemVerilog and simulation concepts.
Familiarity with STA, timing constraints, and physical implementation considerations is an advantage.
Strong debugging and problem-solving skills.
Good communication and ability to work effectively in a collaborative engineering environment.
Education
B.E./B.Tech/M.E./M.Tech in Electrical Engineering, Electronics & Communication, VLSI, or a related discipline.
Preferred Experience
Candidates with experience in one or more of the following areas will be preferred:
Advanced DFT architecture and implementation
ATPG and fault coverage optimization
Scan compression
MBIST/LBIST
JTAG / Boundary Scan
DFT verification and pattern debug
SoC-level DFT integration
DFT timing and physical-design considerations
Apply Now
Interested candidates can share their updated resume at:
📩 [email protected]
Show more Show less
Location: Bangalore, India
Experience: 2–8 Years
Employment Type: Full-time
About the Role
Truechip is looking for a highly motivated DFT Engineer to join our engineering team. The role involves working on Design-for-Test (DFT) architecture, implementation, verification, and debug for complex SoC and IP designs.
The ideal candidate should have strong fundamentals in digital design and hands-on experience with DFT methodologies, including scan insertion, ATPG, MBIST, JTAG, and test coverage analysis.
Key Responsibilities
Develop and implement DFT architectures for complex SoC/IP designs.
Perform scan insertion, scan stitching, and DFT rule checking.
Develop and analyze ATPG patterns and improve fault coverage.
Work on stuck-at, transition, and other production fault models.
Implement and verify MBIST/LBIST solutions.
Work on JTAG / IEEE 1149.1 Boundary Scan and related test architectures.
Perform DFT verification, simulation, pattern validation, and debug.
Analyze DFT-related violations and resolve implementation issues.
Collaborate with RTL, Design Verification, Physical Design, and SoC teams.
Debug test coverage, timing, scan-chain, and pattern-related issues.
Support DFT sign-off and contribute to improving test quality and coverage.
Participate in customer engagements and provide technical support when required.
Required Skills
Strong understanding of Digital Design and DFT concepts.
Hands-on experience with Scan, ATPG, MBIST, LBIST, and JTAG.
Good knowledge of fault models and fault coverage analysis.
Experience with DFT/ATPG tools such as Synopsys TestMAX/TetraMAX, Siemens Tessent, Cadence Modus, or equivalent.
Understanding of scan compression, EDT, test modes, and test clocks.
Good knowledge of Verilog/SystemVerilog and simulation concepts.
Familiarity with STA, timing constraints, and physical implementation considerations is an advantage.
Strong debugging and problem-solving skills.
Good communication and ability to work effectively in a collaborative engineering environment.
Education
B.E./B.Tech/M.E./M.Tech in Electrical Engineering, Electronics & Communication, VLSI, or a related discipline.
Preferred Experience
Candidates with experience in one or more of the following areas will be preferred:
Advanced DFT architecture and implementation
ATPG and fault coverage optimization
Scan compression
MBIST/LBIST
JTAG / Boundary Scan
DFT verification and pattern debug
SoC-level DFT integration
DFT timing and physical-design considerations
Apply Now
Interested candidates can share their updated resume at:
📩 [email protected]
Show more Show less