TH
DFT Engineer
Accepting applicationsTalAstra HR Consultants Private Limited · Bengaluru, Karnataka, India
Full-Time Mid_senior ATEATPGBoundary ScanCadenceDFT
Posted
6d ago
Category
Test
Experience
Mid_senior
Country
India
DFT Engineer
Location-Bangalore
Experience 5- 10 years
Notice Period- Immediate
Qualification-Btech
About the Rol
e
We are looking for an experienced DFT Engineer with strong hands-on expertise in DFT implementation, verification and debug. The ideal candidate should have extensive experience with Tessent-based DFT flows, Scan Insertion, ATPG, MBIST, GLS debug, and DFT verification. The candidate should be capable of independently driving DFT activities from specification through implementation and verificatio
n.
Responsibilit
ies
Develop and implement DFT architecture and specificati
ons.Perform DFT RTL insertion, DRC checks, and clos
ure.Execute Scan Insertion, ATPG, MBIST, and JTAG implementat
ion.Generate, validate, and debug ATPG and MBIST patte
rns.Perform and debug Gate-Level Simulations (G
LS).Work closely with Design, Verification, Physical Design, and Silicon Validation te
ams.Analyze test coverage, optimize test quality, and reduce test t
ime.Support silicon bring-up, failure analysis, and production test activit
ies.
Qualific
ations
Minimum 5+ years of relevant industry experience
in DFT.Hands-on experience in DFT architecture, implementation, verification and
debug.Experience working independently and driving DFT tasks to c
losure.
Requir
ed Skills
Strong hands-on experience with Mentor Tessent
DFT flow.Expertise in Tessent TestCompress/Tes
tKompress.Hands-on experience in Tessent DFT RTL insertion, DRC checks,
and debug.Experience in Scan Insertion, Scan Architecture, and Scan Ch
ain Debug.Hands-on experience in ATPG pattern generation, compressed ATPG, and patt
ern debug.Experience in MBIST insertion, pattern generation, validation,
and debug.Experience with Gate Level Simulation (GLS), including timing-enabled GLS and rela
ted debug.Good understanding of JTAG, Boundary Scan, IEEE 1500, and IJTAG (I
EEE 1687).Strong Verilog knowledge and simulation/debug e
xperience.Experience using Cadence NCSim/Xcelium for DFT ver
ification.Ability to debug ATPG, MBIST, JTAG, and GLS-relat
ed issues.
Pref
erred Skills
Mentor Tessent LBIST insertion and
verification.Silicon debug and failure analysi
s experience.ATE data analys
is and debug.Experience with Cadence G
enus and LEC.Working knowledge of
SpyGlass DFT.TCL scripting for DFT automati
on and debug.Knowledge of AMBA protoco
ls is a plus
.
Warm RegardsMa
ry Marga Reeta.SAssistant Manager-Recruitment & Busi
ness Developmentree
ta.s@talastra.i
nwww.Talastra.inhttps://www.linkedin.com/company/talastr
a-hr-consultant/
Show more Show less
Location-Bangalore
Experience 5- 10 years
Notice Period- Immediate
Qualification-Btech
About the Rol
e
We are looking for an experienced DFT Engineer with strong hands-on expertise in DFT implementation, verification and debug. The ideal candidate should have extensive experience with Tessent-based DFT flows, Scan Insertion, ATPG, MBIST, GLS debug, and DFT verification. The candidate should be capable of independently driving DFT activities from specification through implementation and verificatio
n.
Responsibilit
ies
Develop and implement DFT architecture and specificati
ons.Perform DFT RTL insertion, DRC checks, and clos
ure.Execute Scan Insertion, ATPG, MBIST, and JTAG implementat
ion.Generate, validate, and debug ATPG and MBIST patte
rns.Perform and debug Gate-Level Simulations (G
LS).Work closely with Design, Verification, Physical Design, and Silicon Validation te
ams.Analyze test coverage, optimize test quality, and reduce test t
ime.Support silicon bring-up, failure analysis, and production test activit
ies.
Qualific
ations
Minimum 5+ years of relevant industry experience
in DFT.Hands-on experience in DFT architecture, implementation, verification and
debug.Experience working independently and driving DFT tasks to c
losure.
Requir
ed Skills
Strong hands-on experience with Mentor Tessent
DFT flow.Expertise in Tessent TestCompress/Tes
tKompress.Hands-on experience in Tessent DFT RTL insertion, DRC checks,
and debug.Experience in Scan Insertion, Scan Architecture, and Scan Ch
ain Debug.Hands-on experience in ATPG pattern generation, compressed ATPG, and patt
ern debug.Experience in MBIST insertion, pattern generation, validation,
and debug.Experience with Gate Level Simulation (GLS), including timing-enabled GLS and rela
ted debug.Good understanding of JTAG, Boundary Scan, IEEE 1500, and IJTAG (I
EEE 1687).Strong Verilog knowledge and simulation/debug e
xperience.Experience using Cadence NCSim/Xcelium for DFT ver
ification.Ability to debug ATPG, MBIST, JTAG, and GLS-relat
ed issues.
Pref
erred Skills
Mentor Tessent LBIST insertion and
verification.Silicon debug and failure analysi
s experience.ATE data analys
is and debug.Experience with Cadence G
enus and LEC.Working knowledge of
SpyGlass DFT.TCL scripting for DFT automati
on and debug.Knowledge of AMBA protoco
ls is a plus
.
Warm RegardsMa
ry Marga Reeta.SAssistant Manager-Recruitment & Busi
ness Developmentree
ta.s@talastra.i
nwww.Talastra.inhttps://www.linkedin.com/company/talastr
a-hr-consultant/
Show more Show less