DFT Engineer

Job Summary
We are looking for an experienced DFT Engineer with 5+ years of hands-on experience in Design-for-Test (DFT) implementation and verification for complex ASIC/SoC designs. The ideal candidate should have strong expertise in scan insertion, ATPG, MBIST, JTAG/IJTAG, DFT verification, and test pattern generation/validation.
The candidate will be responsible for executing DFT activities from specification and architecture through implementation, verification, pattern generation, and sign-off.
Key Responsibilities
Develop and implement DFT architecture for complex ASIC/SoC designs.
Perform scan insertion, scan compression, ATPG, and test pattern generation.
Work on MBIST/LBIST implementation and verification.
Implement and debug JTAG, IJTAG, boundary scan, and test access mechanisms.
Develop and validate DFT constraints and ensure DFT rule compliance.
Perform DFT simulations and debug test-related issues.
Validate ATPG patterns and analyze fault coverage.
Work closely with RTL, Design Verification, Physical Design, STA, and other teams to resolve DFT-related issues.
Support DFT integration at block and full-chip levels.
Analyze and improve stuck-at, transition, and other fault coverage metrics.
Debug scan chain, compression, clock, reset, and test-mode issues.
Support DFT timing and physical implementation requirements.
Participate in DFT sign-off activities and provide required reports and documentation.
Automate DFT flows and reporting using TCL, Perl, Python, or Shell scripting.
Support post-silicon test/debug activities when required.
Required Skills
5+ years of relevant DFT/ASIC experience.
Strong hands-on experience with:
Scan insertion
ATPG
Scan compression
MBIST
JTAG / IJTAG
Boundary Scan
DFT verification
Good understanding of ASIC/SoC design and DFT methodologies.
Experience with DFT tools from Synopsys, Cadence, Siemens EDA/Mentor, or equivalent.
Strong knowledge of ATPG fault models and coverage analysis.
Experience with simulation and pattern validation.
Good understanding of test clocks, test modes, scan chains, resets, and clock-domain considerations.
Strong debugging and problem-solving skills.
Good scripting knowledge in TCL / Python / Perl / Shell.
Ability to work effectively with cross-functional semiconductor design teams.
Good to Have
Experience with advanced DFT architectures and large SoCs.
Exposure to hierarchical DFT implementation and full-chip integration.
Experience with IEEE 1149.1, IEEE 1500, and IEEE 1687 (IJTAG).
Knowledge of low-power DFT methodologies.
Experience with DFT requirements for advanced technology nodes.
Exposure to physical-design-aware DFT implementation.
Experience with DFT sign-off and silicon bring-up/debug.
Education
Bachelor's or Master's degree in Electronics & Communication Engineering, Electrical Engineering, Microelectronics, or a related field.
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