DFT Engineer

We are seeking a highly motivated DFT Debug Verification Engineer to join our Silicon Verification team. The ideal candidate will be responsible for enabling and verifying debug features across both pre-silicon and post-silicon environments. This role requires strong expertise in SystemVerilog-based verification, netlist-level connectivity, and scan/JTAG-based debug methodologies.

You will collaborate closely with Design, DFT, DV, Emulation, and Silicon Validation teams to ensure robust implementation and verification of debug infrastructure, including scan chains, JTAG interfaces, and related test logic.

Key Responsibilities

• Develop and execute verification plans for DFT debug features at block and full-chip levels.
• Perform netlist-level connectivity checks and debug issues related to scan dump.
• Analyze and debug scan chain failures at the scan cell level.
• Validate debug features such as scan dump, reset control, clock gating, and test access mechanisms.
• Work on JTAG protocol validation and TAP controller-based test access paths.
• Develop and maintain RTL + Netlist SystemVerilog-based testbench components for debug feature verification.
• Collaborate with DFT and Design teams to resolve structural and functional issues at RTL and gate-level.
• Perform root-cause analysis of DFT-related failures during simulation or silicon bring-up.
• Support post-silicon debug by correlating simulation and tester (ATE) data.
• Review netlist connectivity and assist in identifying test coverage gaps or implementation issues.

Education, Skills & Experience

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field.
• 6+ years of experience enabling and verifying debug features across pre-silicon and post-silicon environments.
• Strong proficiency in SystemVerilog and verification methodologies.
• Experience with netlist-level verification and debugging.
• Solid understanding of DFT concepts including scan chains, boundary scan, and test modes.
• Hands-on experience with JTAG protocol and scan architecture.
• Experience debugging issues at the scan cell level.
• Familiarity with simulation tools and waveform analysis.
• Strong analytical and problem-solving skills.