DFT Engineer

We are seeking a highly skilled CAD Engineer specializing in Design-for-Test (DFT) to collaborate with global, multi-functional teams and EDA vendors. The ideal candidate will design and optimize advanced DFT flows for next-generation complex products, including:

• Developing Spyglass-based DFT (TestMax) scan DRC analysis and scan coverage estimation flows at the RTL level.
• Creating SiliconInsight-based pattern generation, test bring-up, debug, and silicon characterization flows.
• Driving innovation in test coverage, yield improvement, and silicon debug methodologies.

Key Responsibilities

• Implement and optimize scan insertion flows.
• Perform coverage loss analysis (stuck-at, transition delay, path delay) and propose solutions to improve test coverage.
• Collaborate on silicon debug and diagnostic platforms for failure analysis and yield improvement.
• Contribute to functional safety, clock domain crossing analysis, and logic synthesis.

Education, Skills & Experience

• Expert-level proficiency with Spyglass DFT for DRC checks and rule sets.
• Extensive hands-on experience with Mentor Tessent, particularly Tessent MBIST (memory BIST insertion, verification, and pattern generation).
• Strong familiarity with SiliconInsight tools for silicon debug and diagnostics.
• Deep understanding of DFT architectures: Scan, JTAG, Boundary Scan, ATPG, MBIST.
• Proficiency in Verilog/VHDL for RTL design.
• Strong scripting skills (Python, Tcl) for automation and flow development.
• Experience implementing EDT, SSN, boundary scan, JTAG/IJTAG features.
• Knowledge of industry-standard simulation tools and Verdi for debug.
• Experience with revision control systems (Git, Perforce).
• Solid background in functional safety and DFT coverage analysis.