QG
DFT Engineer
Accepting applicationsQuest Global · San Jose, CA
Full-Time Mid_senior ATEATPGDFTJTAGSynopsys
Posted
6d ago
Category
Test
Experience
Mid_senior
Country
United States
Quest Global is hiring for an experienced engineer for DFT Engineer job position. Below is the job ask ::
Location: San Jose,CA
Minimum qualifications:
Bachelor’s degree in electrical engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
7+ years of experience in DFT architecture, implementation, ATPG, and verification for SoCs.
Experience with industry-standard test methodologies and platforms, such as (but not limited to) ATE, MBIST, JTAG, or System Level Test (SLT).
Preferred qualifications:
Master's degree or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
Experience in DFT flow, including architecture, IP integration (Test controllers, TAP, MBIST), and interaction with synthesis and verification flows.
Experience with industry-leading EDA tools for DFT, such as Synopsys (e.g., Design Compiler, DFT Max) or Siemens EDA (e.g., Tessent, TestKompress).
Experience with silicon process and technology nodes for high speed and low power consumption.
Experience with various fault models (e.g., Stuck-at, Transition, Cell-Aware, Path Delay, etc.).
Responsibilities:
Complete all Test Design Rule Checks and Design changes to fix TDRC violations to achieve high test quality.
Insert DFT logic, including scan chains, MBIST, TAP controller, Clock Control block, and other DFT IP blocks.
Insert and hook up MBIST logic including test collar around memories, MBIST controllers, eFuse logic and connect to core and TAP interfaces.
Design Verification of DFT logic and test pattern generation.
Design and Implement System Level Test strategy.
If interested, please share your resume at shashank.verma@quest-global.com.
With Regard
sShashank Verm
a
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Location: San Jose,CA
Minimum qualifications:
Bachelor’s degree in electrical engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
7+ years of experience in DFT architecture, implementation, ATPG, and verification for SoCs.
Experience with industry-standard test methodologies and platforms, such as (but not limited to) ATE, MBIST, JTAG, or System Level Test (SLT).
Preferred qualifications:
Master's degree or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
Experience in DFT flow, including architecture, IP integration (Test controllers, TAP, MBIST), and interaction with synthesis and verification flows.
Experience with industry-leading EDA tools for DFT, such as Synopsys (e.g., Design Compiler, DFT Max) or Siemens EDA (e.g., Tessent, TestKompress).
Experience with silicon process and technology nodes for high speed and low power consumption.
Experience with various fault models (e.g., Stuck-at, Transition, Cell-Aware, Path Delay, etc.).
Responsibilities:
Complete all Test Design Rule Checks and Design changes to fix TDRC violations to achieve high test quality.
Insert DFT logic, including scan chains, MBIST, TAP controller, Clock Control block, and other DFT IP blocks.
Insert and hook up MBIST logic including test collar around memories, MBIST controllers, eFuse logic and connect to core and TAP interfaces.
Design Verification of DFT logic and test pattern generation.
Design and Implement System Level Test strategy.
If interested, please share your resume at shashank.verma@quest-global.com.
With Regard
sShashank Verm
a
Show more Show less