PS
DFT Engineer
Accepting applicationsPi Square Technologies · Santa Clara, CA
Full-Time Mid_senior ASICATPGBISTBoundary ScanDFT
Posted
3d ago
Category
Test
Experience
Mid_senior
Country
United States
Job Description
We are seeking a highly skilled DFT Engineer with strong expertise in Design-for-Test methodologies and implementation for complex ASIC/SoC designs. The ideal candidate will have hands-on experience with DFT architecture, implementation, verification, and silicon bring-up activities. ATPG experience is not mandatory; however, strong DFx and DFT implementation skills are required.
### Key Responsibilities
* Implement and integrate DFT features including Scan, MBIST, JTAG, Boundary Scan, and IJTAG architectures.
* Perform DFT insertion for Scan chains (including SSN) and Memory BIST (MBIST).
* Implement and verify MBIST repair solutions and memory repair methodologies.
* Generate and deliver DFT collaterals required for Test Timing Analysis and Physical Design (Place & Route) teams.
* Develop, validate, and maintain DFT specifications and implementation documentation.
* Verify DFT functionality through simulation and validation of:
* Boundary Scan
* JTAG
* Scan
* MBIST
* High-Speed I/O interfaces
* Work closely with Design, Verification, Physical Design, and Product Engineering teams to ensure successful DFT integration and tape-out readiness.
* Support silicon bring-up, debug, and production test activities.
### Required Skills
* Strong understanding of Design-for-Test (DFT) methodologies and ASIC/SoC test architectures.
* Hands-on experience with Siemens/Mentor Graphics DFT tool suite.
* Expertise in:
* Scan Insertion and Scan Architecture
* SSN (Streaming Scan Network)
* MBIST Implementation and Verification
* MBIST Repair Implementation
* Boundary Scan and JTAG
* IJTAG (IEEE 1687) standards
* Strong knowledge of ICL (Instrument Connectivity Language) and PDL (Procedural Description Language) specifications.
* Experience generating DFT collateral for timing closure and physical design flows.
* Proficiency in Verilog/SystemVerilog and simulation/debug environments.
* Strong debugging and problem-solving skills.
### Preferred Qualifications
* Experience with advanced SoC/ASIC designs.
* Knowledge of high-speed interface testing methodologies.
* Familiarity with silicon validation and post-silicon debug activities.
* Understanding of low-power DFT concepts and methodologies.
### Education
* Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related field.
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We are seeking a highly skilled DFT Engineer with strong expertise in Design-for-Test methodologies and implementation for complex ASIC/SoC designs. The ideal candidate will have hands-on experience with DFT architecture, implementation, verification, and silicon bring-up activities. ATPG experience is not mandatory; however, strong DFx and DFT implementation skills are required.
### Key Responsibilities
* Implement and integrate DFT features including Scan, MBIST, JTAG, Boundary Scan, and IJTAG architectures.
* Perform DFT insertion for Scan chains (including SSN) and Memory BIST (MBIST).
* Implement and verify MBIST repair solutions and memory repair methodologies.
* Generate and deliver DFT collaterals required for Test Timing Analysis and Physical Design (Place & Route) teams.
* Develop, validate, and maintain DFT specifications and implementation documentation.
* Verify DFT functionality through simulation and validation of:
* Boundary Scan
* JTAG
* Scan
* MBIST
* High-Speed I/O interfaces
* Work closely with Design, Verification, Physical Design, and Product Engineering teams to ensure successful DFT integration and tape-out readiness.
* Support silicon bring-up, debug, and production test activities.
### Required Skills
* Strong understanding of Design-for-Test (DFT) methodologies and ASIC/SoC test architectures.
* Hands-on experience with Siemens/Mentor Graphics DFT tool suite.
* Expertise in:
* Scan Insertion and Scan Architecture
* SSN (Streaming Scan Network)
* MBIST Implementation and Verification
* MBIST Repair Implementation
* Boundary Scan and JTAG
* IJTAG (IEEE 1687) standards
* Strong knowledge of ICL (Instrument Connectivity Language) and PDL (Procedural Description Language) specifications.
* Experience generating DFT collateral for timing closure and physical design flows.
* Proficiency in Verilog/SystemVerilog and simulation/debug environments.
* Strong debugging and problem-solving skills.
### Preferred Qualifications
* Experience with advanced SoC/ASIC designs.
* Knowledge of high-speed interface testing methodologies.
* Familiarity with silicon validation and post-silicon debug activities.
* Understanding of low-power DFT concepts and methodologies.
### Education
* Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related field.
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