DFT Engineer

About the company:
Our client is a rapidly growing semiconductor engineering and technology services organization delivering end-to-end solutions to global technology companies. With expertise spanning ASIC design, verification, physical design, DFT, circuit design and layout, FPGA design, and emulation, the organization supports customers across the semiconductor development lifecycle. Known for its focus on engineering excellence, innovation, high-quality delivery, and shorter development cycles, the company provides professionals with opportunities to work on challenging, next-generation semiconductor technologies in a collaborative and growth-oriented environment.

Job Summary:
We are looking for an experienced DFT Engineer to drive the design-for-test architecture, DFT insertion, integration, and signoff for full-chip designs, including PHYs and third-party IPs. The role will involve implementing and validating scan, compression, BIST, MBIST, ATPG, JTAG, and boundary-scan capabilities across complex multi-clock digital designs, with a strong focus on automotive-grade test requirements.

Key Responsibilities:
Define and implement DFT architecture and test strategies for full-chip designs, including PHY and third-party IP integration.
Perform scan chain insertion and scan compression across multi-clock digital logic using Siemens Tessent.
Integrate and validate ASA PHY DFT and associated DFT interfaces.
Handle ASA IP DFT port integration and ensure proper connectivity and functionality.
Implement BIST PCS-PMA bus isolation as part of the overall DFT architecture.
Develop and integrate Memory BIST (MBIST) solutions for internal SRAMs and FIFOs.
Perform ATPG pattern generation and fault simulation to achieve the required test coverage.
Integrate IEEE 1149.1 JTAG controllers and implement boundary-scan functionality.
Support boundary-scan implementation with a focus on automotive test coverage.
Work with DFT tools such as Siemens Tessent and/or Synopsys DFT Compiler.
Support DFT verification, debugging, coverage analysis, and signoff activities.
Ensure DFT modes and implementation meet the coverage requirements specified by the client.
Collaborate with RTL, physical design, verification, PHY, and IP teams to resolve DFT integration and implementation issues.
Contribute to DFT implementation aligned with automotive-grade quality and reliability requirements.

Required Technical Skills:
Strong experience in DFT architecture, insertion, integration, and signoff.
Hands-on experience with scan chain insertion and compression using Tessent.
Experience working with multi-clock digital logic.
Experience in PHY DFT integration and DFT port implementation.
Good understanding of BIST, MBIST, ATPG, fault simulation, and test coverage.
Experience with SRAM/FIFO MBIST implementation.
Strong knowledge of IEEE 1149.1 JTAG and boundary scan.
Experience with Siemens Tessent and/or Synopsys DFT Compiler.
Understanding of full-chip DFT integration involving PHYs and third-party IPs.
Exposure to automotive-grade DFT requirements is preferred.

Automotive Experience:
Prior experience in automotive-grade DFT, particularly designs developed in accordance with AEC-Q100-oriented requirements, will be preferred.

Qualifications & Experience:
B.E. / B.Tech / M.E. / M.Tech in Electronics, Electrical Engineering, VLSI, or related discipline.
7–8 years of relevant DFT experience.
Candidates with hands-on experience in automotive semiconductor projects will be preferred.

Travel:
Travel requirements will be based on client/project requirements.

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