LT
DFT Engineer
Accepting applicationsLorven Technologies Inc. · Santa Clara, CA
Full-Time Mid_senior ASICATPGDFTRTLSoC
Posted
5d ago
Category
Test
Experience
Mid_senior
Country
United States
Our client is looking DFT Engineer for Fulltime project in Santa Clara, CA (Onsite) Below is the detail requirement.
Job Title: DFT Enginee
rLocation: Santa Clara, C
A
Required Skills & Qualificatio
ns• 5+ years of hands-on experience in DFT and ATPG for SoC or ASIC desig
ns• Strong understanding of DFT fundamentals including controllability, observability, and scan-based testi
ng• Proven expertise in ATPG pattern generation, analysis, and deb
ug• Experience with MBIST, including memory test architectures and diagnosti
cs• Knowledge of IO Test methodologies for interface and pin level validati
on• Solid understanding of clock DFT and clock verification concep
ts• Strong grasp of digital design and RTL fundamenta
ls• Experience with industry standard DFT/ATPG EDA too
ls• Ability to work effectively in fast paced, high performance semiconductor progra
ms• Strong analytical, problem solving, and communication skil
ls
pls source the candidates for the below revised JD. More of the DFx skills and other DFT skills are require
d. Familiarity with the Siemens suite of DFT to
olsDFT insertion for SCAN (with SSN) and MB
ISTMBIST Repair Implementation and Verificat
ionGenerating collaterals for Test Timing and Place and Ro
uteExpertise in IJTAG 1687 standard and good at understanding ICL and PDL standard S
pecVerification of DFT features, includ
ingBoundary S
canJ
TAGS
CANMB
ISTHigh Speed
IO
Show more Show less
Job Title: DFT Enginee
rLocation: Santa Clara, C
A
Required Skills & Qualificatio
ns• 5+ years of hands-on experience in DFT and ATPG for SoC or ASIC desig
ns• Strong understanding of DFT fundamentals including controllability, observability, and scan-based testi
ng• Proven expertise in ATPG pattern generation, analysis, and deb
ug• Experience with MBIST, including memory test architectures and diagnosti
cs• Knowledge of IO Test methodologies for interface and pin level validati
on• Solid understanding of clock DFT and clock verification concep
ts• Strong grasp of digital design and RTL fundamenta
ls• Experience with industry standard DFT/ATPG EDA too
ls• Ability to work effectively in fast paced, high performance semiconductor progra
ms• Strong analytical, problem solving, and communication skil
ls
pls source the candidates for the below revised JD. More of the DFx skills and other DFT skills are require
d. Familiarity with the Siemens suite of DFT to
olsDFT insertion for SCAN (with SSN) and MB
ISTMBIST Repair Implementation and Verificat
ionGenerating collaterals for Test Timing and Place and Ro
uteExpertise in IJTAG 1687 standard and good at understanding ICL and PDL standard S
pecVerification of DFT features, includ
ingBoundary S
canJ
TAGS
CANMB
ISTHigh Speed
IO
Show more Show less