I-
DFT Engineer
Accepting applicationsIntelliswift - An LTTS Company · San Francisco Bay Area
Full-Time Mid_senior ATPGBoundary ScanBoundary scanDFTJTAG
Posted
3d ago
Category
Test
Experience
Mid_senior
Country
United States
Role: DFT Engineer (Design-for-Test)
Fulltime role with L&T Technology Services (LTTS)
Location: Santa Clara, CA, California – Onsite
Summary:
DFT Engineers with strong expertise in Design-for-Test (DFT) and DFx verification to support advanced semiconductor programs. The role focuses on DFT implementation, integration, and verification of DFT features across complex SoCs.
Key Responsibilities
• Perform DFT insertion and integration for:
• Scan (including SSN architectures)
• MBIST
Own DFT verification (DFx focus) across:
Boundary Scan
• JTAG
• SCAN
• MBIST
• High-Speed IO interfaces
• Execute MBIST implementation and repair flows, including:
• Repair architecture integration
• Verification and validation
• Work on IJTAG (IEEE 1687):
• Develop and validate ICL and PDL descriptions
• Ensure compliance with IJTAG standards
Generate and support DFT collaterals for:
• Test timing
• Physical design (Place & Route)
• Collaborate with design, verification, and physical implementation teams to ensure robust DFT architecture and closure
Required Skills & Expertise
• Strong hands-on experience in DFT methodologies and flows
• Expertise in DFx (Design-for-X) with focus on DFT verification
Solid knowledge of:
• Scan insertion and debugging
• MBIST architecture and verification
• Boundary scan and JTAG protocols
• Experience with IJTAG (1687), ICL, and PDL standards
• Familiarity with high-speed IO test methodologies
• Experience working with DFT tools (preferably Siemens/Tessent suite)
• Good understanding of test timing and physical design impact on DFT
Nice to Have
• Exposure to large SoC environments and advanced nodes
• Experience in cross-functional debug and silicon bring-up
• Prior experience with automation or scripting (Python/Perl)
• ATPG experience
Experience
• 5+ years of relevant DFT experience
• Greater emphasis is placed on:
• DFx capabilities
• DFT feature verification expertise
Ideal Candidate Profile
• Strong in DFT fundamentals with hands-on implementation
• Deep experience in DFT verification and DFx flows
• Comfortable working in fast-paced, high-quality silicon development environments
Show more Show less
Fulltime role with L&T Technology Services (LTTS)
Location: Santa Clara, CA, California – Onsite
Summary:
DFT Engineers with strong expertise in Design-for-Test (DFT) and DFx verification to support advanced semiconductor programs. The role focuses on DFT implementation, integration, and verification of DFT features across complex SoCs.
Key Responsibilities
• Perform DFT insertion and integration for:
• Scan (including SSN architectures)
• MBIST
Own DFT verification (DFx focus) across:
Boundary Scan
• JTAG
• SCAN
• MBIST
• High-Speed IO interfaces
• Execute MBIST implementation and repair flows, including:
• Repair architecture integration
• Verification and validation
• Work on IJTAG (IEEE 1687):
• Develop and validate ICL and PDL descriptions
• Ensure compliance with IJTAG standards
Generate and support DFT collaterals for:
• Test timing
• Physical design (Place & Route)
• Collaborate with design, verification, and physical implementation teams to ensure robust DFT architecture and closure
Required Skills & Expertise
• Strong hands-on experience in DFT methodologies and flows
• Expertise in DFx (Design-for-X) with focus on DFT verification
Solid knowledge of:
• Scan insertion and debugging
• MBIST architecture and verification
• Boundary scan and JTAG protocols
• Experience with IJTAG (1687), ICL, and PDL standards
• Familiarity with high-speed IO test methodologies
• Experience working with DFT tools (preferably Siemens/Tessent suite)
• Good understanding of test timing and physical design impact on DFT
Nice to Have
• Exposure to large SoC environments and advanced nodes
• Experience in cross-functional debug and silicon bring-up
• Prior experience with automation or scripting (Python/Perl)
• ATPG experience
Experience
• 5+ years of relevant DFT experience
• Greater emphasis is placed on:
• DFx capabilities
• DFT feature verification expertise
Ideal Candidate Profile
• Strong in DFT fundamentals with hands-on implementation
• Deep experience in DFT verification and DFx flows
• Comfortable working in fast-paced, high-quality silicon development environments
Show more Show less