HT
DFT Engineer
Accepting applicationsHighbrow Technology Inc · San Francisco Bay Area
Full-Time Mid_senior ATPGDFTJTAGPerlTcl
Posted
1d ago
Category
Test
Experience
Mid_senior
Country
United States
Hiring: DFT Engineer (Design for Test)
Location: Bay Area, CA (Onsite)
Experience: 8+ Years
Type: Full Time opportunity
We are looking for an experienced DFT Engineer to join our team in the Bay Area. The ideal candidate should have strong expertise in DFT architecture, scan implementation, ATPG, MBIST, and timing closure for advanced semiconductor designs.
Required Skills:
8+ years of industry experience in Design for Test (DFT)
Strong experience with DFT Architecture
Expertise in Scan Insertion, Test Muxing, ATPG, MBIST, and Pre/Post-Layout Simulation
Experience with Top-Level DFT Switching and DFT architecture
Strong knowledge of Test Clock Strategy & Muxing
Experience with Test Timing Constraints for shift, capture, MBIST, and special test modes, including timing closure
Familiarity with Low Power Testability, including Level Shifters (LS), Isolation (ISO), Retention (RET), and state tables
Experience with JTAG for board-level interconnect testing
Strong programming skills in Tcl and Perl (mandatory)
Experience in DFT Flow Development is a plus
📩 Interested candidates, please share your updated resume at: mohamed@highbrowtechnology.com
Show more Show less
Location: Bay Area, CA (Onsite)
Experience: 8+ Years
Type: Full Time opportunity
We are looking for an experienced DFT Engineer to join our team in the Bay Area. The ideal candidate should have strong expertise in DFT architecture, scan implementation, ATPG, MBIST, and timing closure for advanced semiconductor designs.
Required Skills:
8+ years of industry experience in Design for Test (DFT)
Strong experience with DFT Architecture
Expertise in Scan Insertion, Test Muxing, ATPG, MBIST, and Pre/Post-Layout Simulation
Experience with Top-Level DFT Switching and DFT architecture
Strong knowledge of Test Clock Strategy & Muxing
Experience with Test Timing Constraints for shift, capture, MBIST, and special test modes, including timing closure
Familiarity with Low Power Testability, including Level Shifters (LS), Isolation (ISO), Retention (RET), and state tables
Experience with JTAG for board-level interconnect testing
Strong programming skills in Tcl and Perl (mandatory)
Experience in DFT Flow Development is a plus
📩 Interested candidates, please share your updated resume at: mohamed@highbrowtechnology.com
Show more Show less