DR
DFT Engineer
Accepting applicationsDarwin Resources · Bengaluru South, Karnataka, India
Full-Time Entry DFTScanATPGMBISTJTAG
Estimated market salary
₹8-14 LPA
This is a SiliconBoard market estimate, not an employer-posted salary.
Posted
4d ago
Category
Test
Experience
Entry
Country
India
Company Description : Pan Asia HR Solutions Pvt. Ltd. is a leading talent acquisition and workforce solutions company specializing in recruitment across diverse industries and technology domains. The organization is committed to connecting skilled professionals with top employers through strategic and personalized hiring solutions. By understanding both client requirements and candidate aspirations, Pan Asia delivers quality talent that drives business success while supporting long-term career growth. With a strong focus on professionalism, integrity, and customer satisfaction, the company partners with organizations to build high-performing teams and helps candidates discover rewarding career opportunities.
Role Description
📍 Location: Bengaluru
💼 Experience: 8+ Years
🏢 Work Mode: Work from Office
💼 Employment Type: Permanent
We're looking for an experienced DFT Engineer with strong expertise in VLSI Design for Test (DFT) methodologies. The ideal candidate should have hands-on experience in scan insertion, ATPG, MBIST, JTAG, simulation, and debug, along with exposure to industry-standard DFT tools.
👉 Key Skills: DFT, Scan Insertion, ATPG, MBIST, JTAG, Boundary Scan, DFT DRC, Scan Compression, Fault Coverage, Gate-Level Simulation (GLS), Pattern Generation, Pattern Validation, Debugging, ASIC, SoC
👉 Preferred Tools: Tessent, Tessent TestKompress, Tessent ATPG, Synopsys DFT Compiler, TetraMAX,
Cadence Modus, VCS, Verdi, Xcelium, QuestaSim
📩 Interested? DM me or share your updated resume at clinton@panasiagroup.net
Show more Show less
Role Description
📍 Location: Bengaluru
💼 Experience: 8+ Years
🏢 Work Mode: Work from Office
💼 Employment Type: Permanent
We're looking for an experienced DFT Engineer with strong expertise in VLSI Design for Test (DFT) methodologies. The ideal candidate should have hands-on experience in scan insertion, ATPG, MBIST, JTAG, simulation, and debug, along with exposure to industry-standard DFT tools.
👉 Key Skills: DFT, Scan Insertion, ATPG, MBIST, JTAG, Boundary Scan, DFT DRC, Scan Compression, Fault Coverage, Gate-Level Simulation (GLS), Pattern Generation, Pattern Validation, Debugging, ASIC, SoC
👉 Preferred Tools: Tessent, Tessent TestKompress, Tessent ATPG, Synopsys DFT Compiler, TetraMAX,
Cadence Modus, VCS, Verdi, Xcelium, QuestaSim
📩 Interested? DM me or share your updated resume at clinton@panasiagroup.net
Show more Show less