C
DFT Engineer
Accepting applicationsCyient · Bengaluru, Karnataka, India
Full-Time Mid DFTJTAGATPGMBISTScan
Estimated market salary
₹9-15 LPA
This is a SiliconBoard market estimate, not an employer-posted salary.
Posted
19h ago
Category
Test
Experience
Mid
Country
India
Should have worked hands-on extensively on Block level and full chip DFT design, implementation, vector generation/verification, JTAG, boundary scan and simulation.
Experience with Scan, Compression, ATPG and simulations with Cadence tools. Logic BIST & MBIST knowledge is must.
Should have participated in successful tape outs of SoC/ASIC automotive chips and achieved test targets.
Descent understanding of front-end SoC/ASIC design and implementation including Synthesis and STA.
Develop/automate flows and scripts in Perl/Tcl to enhance the DFT methodologies & process
Excellent problem solving and debugging skills. Proactive in nature- Excellent
Communication and Team work skills
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Experience with Scan, Compression, ATPG and simulations with Cadence tools. Logic BIST & MBIST knowledge is must.
Should have participated in successful tape outs of SoC/ASIC automotive chips and achieved test targets.
Descent understanding of front-end SoC/ASIC design and implementation including Synthesis and STA.
Develop/automate flows and scripts in Perl/Tcl to enhance the DFT methodologies & process
Excellent problem solving and debugging skills. Proactive in nature- Excellent
Communication and Team work skills
Show more Show less