C
DFT Engineer
Accepting applicationsChiparama · San Jose, CA
Full-Time Mid_senior ASICATEATPGAnalogBIST
Posted
1d ago
Category
Test
Experience
Mid_senior
Country
United States
Senior DFT Engineer – Full-Time | San Jose, CA
📍 Location: San Jose, California (Onsite)
💼 Employment Type: Full-Time (W2)
💰 Salary: $180,000 – $220,000 /Year
Actual compensation will be determined based on factors such as experience, skills, education, certifications, and business needs. Employees may also be eligible for bonuses, equity, and a comprehensive benefits package.
We are hiring an experienced Senior DFT Engineer to join one of our leading semiconductor clients in San Jose, CA. This role is ideal for engineers passionate about advanced Design-for-Test (DFT) methodologies, silicon bring-up, and next-generation test solutions for cutting-edge process technologies.
Responsibilities
Understand Broadcom and customer DFT feature requirements, DPPM goals, and define appropriate DFT specifications for ASICs.
Implement DFT features including Scan, MBIST, LBIST, TAP, IO DFT, SerDes DFT, and third-party IP integration.
Generate, verify, and debug chip-level ATPG patterns and test vectors before tape-out.
Support rapid silicon bring-up on ATE and provide RMA/debug support.
Collaborate with STA and Design Implementation teams to achieve design closure for test.
Validate and debug test vectors during silicon bring-up.
Perform silicon failure analysis, diagnostics, yield improvement, and quality optimization.
Work closely with customers, Physical Design, Manufacturing, and Test Engineering teams across global locations.
Support debugging of customer-returned silicon on ATE.
Drive innovation in DFT methodologies for advanced nodes (3nm and beyond).
Develop automation to improve DFT implementation and ATPG/test vector generation flows.
Required Qualifications
Bachelor's degree with 12+ years of related experience, or Master's degree with 10+ years of related experience.
Strong expertise in DFT, including:
Scan Architecture
Scan Insertion
ATPG
Scan Compression
MBIST
LBIST
Boundary Scan
TAP Controller
IO & Analog DFT
Hands-on experience with DFT Compiler, Tessent, TestKompress, TetraMAX, FastScan, or equivalent tools.
Experience with Verilog, testbench development, simulation, and debugging.
Memory BIST insertion and verification for embedded memories (SRAM, CAM, eDRAM, ROM).
Strong knowledge of IEEE 1149.1, IEEE 1149.6, IEEE 1687 (IJTAG), ICL, and PDL.
Understanding of Test STA, timing constraints, logical/physical synthesis, and silicon reliability.
Strong analytical, debugging, root cause analysis, and communication skills.
Experience with statistical process control and silicon yield improvement.
Ability to manage multiple priorities across cross-functional engineering teams.
Preferred Qualifications
Experience with ATE validation and silicon debug.
Knowledge of SerDes, DDR, PCIe, Ethernet, CXL IOBIST verification.
Experience with Tessent SSN.
Prior experience working on advanced process nodes (5nm, 3nm, or below).
Equal Employment Opportunity
We are an Equal Opportunity Employer and are committed to creating an inclusive workplace. All qualified applicants will receive consideration for employment without regard to race, color, religion, creed, sex (including pregnancy, childbirth, breastfeeding, or related medical conditions), gender identity, gender expression, sexual orientation, national origin, ancestry, age, disability, medical condition, genetic information, marital status, military or veteran status, citizenship status, or any other status protected by applicable federal, state, or local law.
Qualified applicants with arrest or conviction records will be considered for employment in accordance with the California Fair Chance Act and other applicable laws.
Reasonable accommodations will be provided to qualified individuals with disabilities throughout the recruitment and hiring process.
📩 Interested candidates can send their resume to: deepak.v@chiparama.com
Keywords: DFT Engineer, ASIC DFT, Scan Insertion, ATPG, MBIST, LBIST, Tessent, TestKompress, TetraMAX, FastScan, IJTAG, IEEE 1687, Verilog, Silicon Bring-up, ATE, Semiconductor Jobs, VLSI, San Jose, California
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📍 Location: San Jose, California (Onsite)
💼 Employment Type: Full-Time (W2)
💰 Salary: $180,000 – $220,000 /Year
Actual compensation will be determined based on factors such as experience, skills, education, certifications, and business needs. Employees may also be eligible for bonuses, equity, and a comprehensive benefits package.
We are hiring an experienced Senior DFT Engineer to join one of our leading semiconductor clients in San Jose, CA. This role is ideal for engineers passionate about advanced Design-for-Test (DFT) methodologies, silicon bring-up, and next-generation test solutions for cutting-edge process technologies.
Responsibilities
Understand Broadcom and customer DFT feature requirements, DPPM goals, and define appropriate DFT specifications for ASICs.
Implement DFT features including Scan, MBIST, LBIST, TAP, IO DFT, SerDes DFT, and third-party IP integration.
Generate, verify, and debug chip-level ATPG patterns and test vectors before tape-out.
Support rapid silicon bring-up on ATE and provide RMA/debug support.
Collaborate with STA and Design Implementation teams to achieve design closure for test.
Validate and debug test vectors during silicon bring-up.
Perform silicon failure analysis, diagnostics, yield improvement, and quality optimization.
Work closely with customers, Physical Design, Manufacturing, and Test Engineering teams across global locations.
Support debugging of customer-returned silicon on ATE.
Drive innovation in DFT methodologies for advanced nodes (3nm and beyond).
Develop automation to improve DFT implementation and ATPG/test vector generation flows.
Required Qualifications
Bachelor's degree with 12+ years of related experience, or Master's degree with 10+ years of related experience.
Strong expertise in DFT, including:
Scan Architecture
Scan Insertion
ATPG
Scan Compression
MBIST
LBIST
Boundary Scan
TAP Controller
IO & Analog DFT
Hands-on experience with DFT Compiler, Tessent, TestKompress, TetraMAX, FastScan, or equivalent tools.
Experience with Verilog, testbench development, simulation, and debugging.
Memory BIST insertion and verification for embedded memories (SRAM, CAM, eDRAM, ROM).
Strong knowledge of IEEE 1149.1, IEEE 1149.6, IEEE 1687 (IJTAG), ICL, and PDL.
Understanding of Test STA, timing constraints, logical/physical synthesis, and silicon reliability.
Strong analytical, debugging, root cause analysis, and communication skills.
Experience with statistical process control and silicon yield improvement.
Ability to manage multiple priorities across cross-functional engineering teams.
Preferred Qualifications
Experience with ATE validation and silicon debug.
Knowledge of SerDes, DDR, PCIe, Ethernet, CXL IOBIST verification.
Experience with Tessent SSN.
Prior experience working on advanced process nodes (5nm, 3nm, or below).
Equal Employment Opportunity
We are an Equal Opportunity Employer and are committed to creating an inclusive workplace. All qualified applicants will receive consideration for employment without regard to race, color, religion, creed, sex (including pregnancy, childbirth, breastfeeding, or related medical conditions), gender identity, gender expression, sexual orientation, national origin, ancestry, age, disability, medical condition, genetic information, marital status, military or veteran status, citizenship status, or any other status protected by applicable federal, state, or local law.
Qualified applicants with arrest or conviction records will be considered for employment in accordance with the California Fair Chance Act and other applicable laws.
Reasonable accommodations will be provided to qualified individuals with disabilities throughout the recruitment and hiring process.
📩 Interested candidates can send their resume to: deepak.v@chiparama.com
Keywords: DFT Engineer, ASIC DFT, Scan Insertion, ATPG, MBIST, LBIST, Tessent, TestKompress, TetraMAX, FastScan, IJTAG, IEEE 1687, Verilog, Silicon Bring-up, ATE, Semiconductor Jobs, VLSI, San Jose, California
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