DFT Engineer # 26-14561

Duration: 12 months Contract

Job Description

We are seeking an experienced Senior/Lead DFT Engineer to join our semiconductor design team. The ideal candidate will have strong expertise in Design for Test (DFT) methodologies, including Scan, ATPG, MBIST, JTAG, simulation, and Post-Silicon Diagnosis at both block and SoC levels.
The candidate will play a key role in defining DFT architecture, implementing test solutions, improving test coverage, and supporting silicon bring-up activities.
Experience with Siemens Tessent (including Streaming Scan Network (SSN)/Streaming Scan Architecture) and Synopsys DFT tools is highly preferred.

Responsibilities:

Define, architect, and implement DFT solutions for complex ASIC/SoC designs.
Implement and validate DFT structures at both block and SoC levels.
Generate and verify ATPG patterns to achieve target fault coverage and test quality.
Perform gate-level simulations (GLS) to validate DFT implementation and test patterns.
Develop DFT specifications, methodologies, and implementation flows for complex designs.
Analyze and debug DFT-related issues including scan chain failures, ATPG violations, MBIST failures, low coverage issues, and silicon test failures.
Collaborate closely with RTL, Synthesis, STA, Physical Design, and Verification teams to resolve DFT integration and timing challenges.
Work with Product/Test Engineering teams during silicon bring-up and production ramp-up activities.
Support silicon debug activities by collecting, analyzing, and interpreting failure data to identify root causes and corrective actions.
Drive DFT signoff activities including coverage analysis, pattern validation, and test readiness reviews.
Develop and maintain automation scripts and custom DFT flows using TCL and other scripting languages.

Experience:

8–10+ years of hands-on experience in Design for Test (DFT) for ASIC/SoC designs.
JTAG/Boundary Scan
Compression Techniques
Fault Coverage Analysis
Gate-Level Simulations
Post-Silicon Debug and Diagnosis
Experience implementing DFT solutions from architecture through silicon validation.
Strong understanding of DFT methodologies, industry standards, and best practices.
Proven experience in debugging DFT issues across RTL, netlist, and silicon stages.
Hands-on experience with Siemens Tessent tool suite for:
Scan Insertion
ATPG
Diagnosis
MBIST
SSN (Streaming Scan Network) / SSM
Experience with Synopsys DFT tools and associated implementation flows.
Strong knowledge of synthesis, timing closure, and physical design impacts on DFT implementation.
Proficiency in TCL scripting for automation and flow development.

Skillset:

Hands-on experience with Streaming Scan Network (SSN) / Streaming Scan Architecture (SSA) in Siemens Tessent environments.
Experience with large-scale SoC and multi-core architectures.
Knowledge of advanced DFT techniques including:
Test Compression
Hierarchical DFT
Diagnosis-driven Yield Analysis
Low-Power ATPG
Experience supporting production test and yield improvement initiatives.
Familiarity with semiconductor manufacturing test flows and ATE environments.

Education:

Bachelor's degree in engineering

Additional Qualifications

Shift Hours: 8:00AM -5:00 PM AST

About US Tech Solutions

US Tech Solutions is a global staff augmentation firm providing a wide range of talent on-demand and total workforce solutions. To know more about US Tech Solutions, please visit www.ustechsolutions.com.

US Tech Solutions is an Equal Opportunity Employer. All qualified applicants will receive consideration for employment without regard to race, colour, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.

AI Statement: By applying, you acknowledge that AI-assisted tools may be used during hiring.

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