DFT Director_Hyderabad

Hi All,

Greetings from Eximietas Design...!

Eximietas Hiring DFT Director

Experience: 20+Years.

Location: Bengaluru, Hyderabad, Ahmedabad & Visakhapatnam.

USA Eligibility:
USA: San Jose (Bay Area) / Austin
U.S. Permanent Residents (Green Card holders) only

Job Description:
We are seeking motivated Design for Test (DFT) professionals to join our growing team. Whether
you are a hands-on technical lead or an industry veteran with architectural expertise, we offer roles
that will challenge and grow your skills in advanced silicon testing.
You will be responsible for the end-to-end DFT flow, from RTL to final pattern delivery, across
complex IP, subsystem, and SOC designs.

Core Responsibilities:
 End-to-end ownership of the DFT implementation flow from RTL to final pattern sign-off.
 Scan architecture definition and implementation at RTL and gate level, including EDT and
OCC.
 Execution of block-level ATPG, DRC analysis, and coverage optimization.
 Handling of pattern simulations, including both timing and non-timing simulations.
 SOC-level integration, including pattern retargeting to subsystem and full-chip levels.
 Integration, simulation, and debugging of MBIST, IJTAG, and Boundary Scan (JTAG).
 Independent debugging of DFT simulations and netlist-related issues.
 Close collaboration with design, verification, and physical design teams to ensure DFT
readiness.
 Ownership of DFT sign-off activities and deliverables.

Key Responsibilities:
 Develop and implement robust DFT architectures for IP, subsystem, and SOC designs.
 Perform scan insertion, ATPG generation, and pattern validation at block and top levels.
 Analyze and resolve coverage, DRC, and simulation failures to meet quality targets.
 Define and execute DFT strategies aligned with project requirements and schedules.
 Support pre-silicon and post-silicon test requirements.
 Serve as the DFT point of contact for assigned projects, responsible for verification and test
readiness sign-off.

Technical Requirements:
Must-Have Skills:
 Strong experience in netlist handling and ATPG simulations.
 Proven expertise in block-level and SOC-level pattern retargeting and debugging.
 In-depth understanding of ICL and PDL standards.
 Hands-on experience with at least one major DFT tool suite:
o Siemens Tessent
o Synopsys TestMAX / TetraMAX
o Cadence Modus

Preferred & Advanced Skills:
 Experience with Streaming Scan Network (SSN).
 Knowledge of Analog and Mixed-Signal DFT methodologies.
 Proficiency with SpyGlass for DFT linting and early-stage analysis.
 Exposure to RTL-level DFT insertion and validation.
 Strong scripting skills (TCL, Python, Perl) for automation.

If you are interested in exploring any of these opportunities, please respond with your updated resume and a suitable time to connect.
Thank you for your time and consideration. I look forward to your response.
Referrals are greatly appreciated—please feel free to forward this within your network...!

Best regards,
Maruthy Prasaad
Associate VLSI Manager - Talent Acquisition | Visakhapatnam
Eximietas Design
maruthiprasad.e@eximietas.design
+91 8088969910.
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