LT
DFT Architect
Accepting applicationsLeadSoc Technologies Pvt Ltd · Bengaluru South, Karnataka, India
Full-Time Mid_senior DFTScanATPGMBISTJTAG
Estimated market salary
₹44-79 LPA
This is a SiliconBoard market estimate, not an employer-posted salary.
Posted
3d ago
Category
Test
Experience
Mid_senior
Country
India
Company Description LeadSoc Technologies Pvt Ltd provides cutting-edge engineering design services in VLSI and embedded systems to Semiconductor, Automotive, Telecom, and Consumer Electronics clients. The company delivers end-to-end VLSI solutions from micro-architecture through tape-out and post-silicon support, working on SoC, FPGA, and ASIC platforms across digital, analog, RF, and board design. LeadSoc operates in-house VLSI and embedded software labs equipped with state-of-the-art tools and reference boards, creating an environment for learning, innovation, and proof-of-concept development. Its software practice covers firmware, hardware abstraction, kernel and user space design on x86, ARM, MIPS, and PowerPC architectures, including platform software, middleware, IoT, cloud applications, and validation services. Teams contribute to diagnostics, pre- and post-silicon validation, performance optimization, and migration of stacks from legacy to next-generation platforms.
Role Description The DFT Architect is responsible for defining and driving Design-for-Test strategies and architectures for complex SoCs and ASICs, ensuring high test coverage and robust manufacturability. Day-to-day responsibilities include collaborating with front-end and back-end design teams to integrate DFT features, specifying scan, MBIST, LBIST, and boundary scan structures, and guiding implementation from RTL through synthesis and physical design. The role involves analyzing test coverage, optimizing patterns and test time, working closely with test engineering teams, and supporting pre- and post-silicon validation and debug. The DFT Architect will prepare documentation, review design constraints, mentor engineers on DFT best practices, and contribute to continuous improvement of internal methodologies and flows. This is a full-time, on-site role based in Bengaluru South.
Qualifications
Exp - 15+ years
Strong expertise in DFT methodologies including scan insertion, MBIST, LBIST, boundary scan, and test compression flows.
Hands-on experience with EDA tools for DFT implementation and verification (e.g., Synopsys, Cadence, Mentor/Siemens tools for scan, BIST, ATPG, and fault simulation).
Solid understanding of digital design fundamentals, RTL development (Verilog/SystemVerilog), synthesis, and timing closure for SoC/ASIC designs.
Experience collaborating with physical design, verification, and test engineering teams to integrate and validate DFT features across the design lifecycle.
Knowledge of manufacturing test concepts, ATE environments, test pattern generation and optimization, and yield/coverage analysis.
Bachelor’s or Master’s degree in Electrical Engineering, Electronics, or a related discipline, with relevant industry experience in VLSI/semiconductor design.
Strong problem-solving and debug
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Role Description The DFT Architect is responsible for defining and driving Design-for-Test strategies and architectures for complex SoCs and ASICs, ensuring high test coverage and robust manufacturability. Day-to-day responsibilities include collaborating with front-end and back-end design teams to integrate DFT features, specifying scan, MBIST, LBIST, and boundary scan structures, and guiding implementation from RTL through synthesis and physical design. The role involves analyzing test coverage, optimizing patterns and test time, working closely with test engineering teams, and supporting pre- and post-silicon validation and debug. The DFT Architect will prepare documentation, review design constraints, mentor engineers on DFT best practices, and contribute to continuous improvement of internal methodologies and flows. This is a full-time, on-site role based in Bengaluru South.
Qualifications
Exp - 15+ years
Strong expertise in DFT methodologies including scan insertion, MBIST, LBIST, boundary scan, and test compression flows.
Hands-on experience with EDA tools for DFT implementation and verification (e.g., Synopsys, Cadence, Mentor/Siemens tools for scan, BIST, ATPG, and fault simulation).
Solid understanding of digital design fundamentals, RTL development (Verilog/SystemVerilog), synthesis, and timing closure for SoC/ASIC designs.
Experience collaborating with physical design, verification, and test engineering teams to integrate and validate DFT features across the design lifecycle.
Knowledge of manufacturing test concepts, ATE environments, test pattern generation and optimization, and yield/coverage analysis.
Bachelor’s or Master’s degree in Electrical Engineering, Electronics, or a related discipline, with relevant industry experience in VLSI/semiconductor design.
Strong problem-solving and debug
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