SL
DFT and DV Engineers
Accepting applicationsSEMI LEAF · Bengaluru South, Karnataka, India
Full-Time Entry ARMATPGBISTDDRDFT
Estimated market salary
₹10-17 LPA
This is a SiliconBoard market estimate, not an employer-posted salary.
Posted
19h ago
Category
Test
Experience
Entry
Country
India
We are Hiring DFT and DV Engineers
Experience Required: 2-10 years (Without training or internship)
Location: Bengaluru | Hyderabad
Availability : Immediate to 40 days
“Your reference would be greatly appreciated”
Job Summary [Design Verification] - DV
We are seeking a passionate and experienced Design Verification Engineer.
The ideal candidate will have strong hands-on experience with , UVM methodology, and a solid understanding of SoC/IP-level verification flows.
Good to have GLS, UPF, Low power experience, ARM, Pcie, Ethernet, USB, DDR, Memory
Job Summary [DFT] :
Experience working for Scan insertion and validation.
BIST, MBIST insertion and validation.
ATPG, IP tests and Pattern Validation w/wo Timing, DFT mode timing analysis and sign off.
Experience in various DFT aspects like Scan insertion, MBIST and JTAG, ATPG, Pattern validation at block level as well as Full-chip level
Be responsible for a comprehensive DFT plan and drive the implementation
Work with DFT and cross functional teams
Share your updated CV to vagdevi@semi-leaf.com
Show more Show less
Experience Required: 2-10 years (Without training or internship)
Location: Bengaluru | Hyderabad
Availability : Immediate to 40 days
“Your reference would be greatly appreciated”
Job Summary [Design Verification] - DV
We are seeking a passionate and experienced Design Verification Engineer.
The ideal candidate will have strong hands-on experience with , UVM methodology, and a solid understanding of SoC/IP-level verification flows.
Good to have GLS, UPF, Low power experience, ARM, Pcie, Ethernet, USB, DDR, Memory
Job Summary [DFT] :
Experience working for Scan insertion and validation.
BIST, MBIST insertion and validation.
ATPG, IP tests and Pattern Validation w/wo Timing, DFT mode timing analysis and sign off.
Experience in various DFT aspects like Scan insertion, MBIST and JTAG, ATPG, Pattern validation at block level as well as Full-chip level
Be responsible for a comprehensive DFT plan and drive the implementation
Work with DFT and cross functional teams
Share your updated CV to vagdevi@semi-leaf.com
Show more Show less