Design Verification - SoC, ASIC System Verilog, UVM

Job description:

🔧 Key Responsibilities
Lead and define end‑to‑end verification strategy for complex ASIC/SoC programs
Architect and develop robust UVM-based verification environments and testbenches
Leverage advanced verification methodologies—UVM, Formal Verification, Assertions
Work hands‑on with industry-leading tools (simulators, formal tools, debuggers)
Debug complex failures, perform root-cause analysis, and partner with design teams
Drive code quality, enforce best practices, and participate in design/code reviews
Mentor and guide junior DV engineers; foster a high‑performance technical culture
Stay ahead of emerging verification technologies, tools, and methodologies
Influence the verification roadmap and contribute to technical decision-making
🎓 Qualifications
Master’s (preferred) or Bachelor’s degree in Electrical/Computer Engineering
10+ years of experience in Design Verification for complex ASIC/SoC designs
Hands‑on expertise with UVM, SystemVerilog, Verilog/VHDL, Assertions
Deep understanding of digital design fundamentals
Strong experience with simulators, formal verification tools, and scripting (Perl/Python/Tcl)
Proven track record of leading verification teams and driving project success
Excellent communication, leadership, analytical, and troubleshooting skills
Ability to handle multiple priorities and deliver under aggressive timelines


Magenderan R
Manager - HR Talent Acquisition Group
HCL Tech.,Bangalore
Mobile: 8050996119
Email:Magenderan.r@hcltech.com
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