WA
Design Verification Lead
Accepting applicationsWeekday AI (YC W21) · Bengaluru, Karnataka, India
Full-Time Mid_senior UVMSystemVerilogSoC VerificationGPU VerificationCoverage
Estimated market salary
₹24-44 LPA
This is a SiliconBoard market estimate, not an employer-posted salary.
Posted
19h ago
Category
Verification
Experience
Mid_senior
Country
India
This role is for one of the Weekday's clients
Salary range: Rs 4000000 - Rs 6000000 (ie INR 40-60 LPA)
Min Experience: 10+ years
Location: Bengaluru
JobType: full-time
Requirements
9 to 15 years of experience to drive the verification strategy for next-gen SoC and NVIDIA GPU integrated architectures
Domain : Proven track record of verifying complex SoCs and GPU sub-systems (specifically experience interfacing with or verifying NVIDIA GPU architectures is highly preferred)
Skills : Expertise in SystemVerilog (SV) and UVM architecture, including building testbenches from scratch
Protocols & IPs : Deep understanding of high-speed interconnects, memory controllers (e.g., DDR, HBM), and standard bus protocols (e.g., AXI, ACE, CHI )
Coverage & Sign-off : Expert-level knowledge in defining functional coverage metrics, writing assertions, and debugging code coverage gaps
Tools : Synopsys VCS, Cadence Xcelium, or Siemens Questa and debuggers like Verdi
Must-have Skills
GPU/SOC Verification, System verilog, UVM Architecture
Good-to-have Skills
AXI, ddr
Show more Show less
Salary range: Rs 4000000 - Rs 6000000 (ie INR 40-60 LPA)
Min Experience: 10+ years
Location: Bengaluru
JobType: full-time
Requirements
9 to 15 years of experience to drive the verification strategy for next-gen SoC and NVIDIA GPU integrated architectures
Domain : Proven track record of verifying complex SoCs and GPU sub-systems (specifically experience interfacing with or verifying NVIDIA GPU architectures is highly preferred)
Skills : Expertise in SystemVerilog (SV) and UVM architecture, including building testbenches from scratch
Protocols & IPs : Deep understanding of high-speed interconnects, memory controllers (e.g., DDR, HBM), and standard bus protocols (e.g., AXI, ACE, CHI )
Coverage & Sign-off : Expert-level knowledge in defining functional coverage metrics, writing assertions, and debugging code coverage gaps
Tools : Synopsys VCS, Cadence Xcelium, or Siemens Questa and debuggers like Verdi
Must-have Skills
GPU/SOC Verification, System verilog, UVM Architecture
Good-to-have Skills
AXI, ddr
Show more Show less