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Design Verification Lead
Accepting applicationsleadIC Design Pvt Ltd · India
Full-Time Mid_senior UVMSystemVerilogVerificationFunctional Verification
Estimated market salary
₹18-33 LPA
This is a SiliconBoard market estimate, not an employer-posted salary.
Posted
3d ago
Category
Verification
Experience
Mid_senior
Country
India
Company Description LeadIC Design Pvt Ltd accelerates semiconductor innovation through full-stack VLSI engineering expertise, supporting the complete chip development lifecycle for global semiconductor companies. Founded in 2018, the company has grown into a trusted partner known for deep technical capability, strong execution ownership, and flexible engagement models. With engineering teams across India and Canada, LeadIC delivers high-quality design services tailored for product-focused teams. Its capabilities cover custom, memory and analog layout, analog and mixed-signal circuit design, digital design and RTL development, design verification, physical design, STA, DFT, physical verification, IP characterization, and FPGA-based prototyping. LeadIC emphasizes an engineering culture built on ownership, quality-driven execution, and long-term technical partnerships that help clients achieve silicon success.
Role Description The Design Verification Lead is a full-time, on-site role based in India. This role is responsible for leading verification planning, testbench architecture, and execution for complex SoC and IP-level designs, ensuring comprehensive coverage and high-quality signoff. The Design Verification Lead will define and maintain verification methodologies, coordinate UVM-based testbench development, review specifications, and drive test case creation, regression, and debug. Day-to-day activities include collaborating closely with design, architecture, and physical design teams, tracking verification metrics, managing issue resolution, and mentoring verification engineers to uphold best practices and rigorous processes. The role also involves stakeholder communication on status, risks, and schedules, and contributing to continuous improvement of verification flows and tools.
Qualifications
Strong design verification expertise including UVM-based testbench development, constrained random verification, and coverage-driven methodologies.
Solid experience with digital design and RTL (Verilog/SystemVerilog), micro-architecture understanding, and specification review.
Hands-on proficiency with industry-standard EDA tools for simulation, regression management, and debug (e.g., simulators, waveform viewers).
Knowledge of AMS and mixed-signal verification concepts and familiarity with full-chip verification flows is beneficial.
Ability to lead verification planning, define strategies, track metrics, and manage schedules and risks.
Experience mentoring and guiding verification teams, promoting best practices and structured methodologies.
Strong analytical, problem-solving, and debugging skills, with attention to detail and quality-focused execution.
Effective written and verbal communication skills for cross-functional collaboration and stakeholder reporting.
Bachelor’s or Master’s degree in Electronics, Electrical Engineering, Computer Engineering, or a related field.
Prior experience in VLSI or semiconductor product development environments; exposure to global teams and projects is an advantage.
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Role Description The Design Verification Lead is a full-time, on-site role based in India. This role is responsible for leading verification planning, testbench architecture, and execution for complex SoC and IP-level designs, ensuring comprehensive coverage and high-quality signoff. The Design Verification Lead will define and maintain verification methodologies, coordinate UVM-based testbench development, review specifications, and drive test case creation, regression, and debug. Day-to-day activities include collaborating closely with design, architecture, and physical design teams, tracking verification metrics, managing issue resolution, and mentoring verification engineers to uphold best practices and rigorous processes. The role also involves stakeholder communication on status, risks, and schedules, and contributing to continuous improvement of verification flows and tools.
Qualifications
Strong design verification expertise including UVM-based testbench development, constrained random verification, and coverage-driven methodologies.
Solid experience with digital design and RTL (Verilog/SystemVerilog), micro-architecture understanding, and specification review.
Hands-on proficiency with industry-standard EDA tools for simulation, regression management, and debug (e.g., simulators, waveform viewers).
Knowledge of AMS and mixed-signal verification concepts and familiarity with full-chip verification flows is beneficial.
Ability to lead verification planning, define strategies, track metrics, and manage schedules and risks.
Experience mentoring and guiding verification teams, promoting best practices and structured methodologies.
Strong analytical, problem-solving, and debugging skills, with attention to detail and quality-focused execution.
Effective written and verbal communication skills for cross-functional collaboration and stakeholder reporting.
Bachelor’s or Master’s degree in Electronics, Electrical Engineering, Computer Engineering, or a related field.
Prior experience in VLSI or semiconductor product development environments; exposure to global teams and projects is an advantage.
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