Design Verification Engineer - Power Management Unit (PMU)

This role is for one of the Weekday's clients

Min Experience: 4+ years

Location: Bengaluru

JobType: full-time

We are looking for a highly motivated Design Verification Engineer - Power Management Unit (PMU) with 4-8 years of experience in semiconductor design verification. The ideal candidate will have strong expertise in verifying complex Power Management Unit (PMU) blocks within modem or SoC subsystems, ensuring functional correctness, reliability, and compliance with design specifications. You will work closely with design, architecture, and validation teams to develop robust verification environments and deliver high-quality silicon for next-generation products.

Requirements

Key Responsibilities

Develop and execute comprehensive verification plans for Power Management Unit (PMU) blocks within modem subsystems
Design, build, and maintain reusable verification environments using SystemVerilog (SV) and Universal Verification Methodology (UVM)
Create constrained-random and directed test cases to verify complex power management features, state transitions, and functional scenarios
Perform block-level and subsystem-level verification while ensuring complete functional coverage
Execute Gate-Level Simulations (GLS) to validate timing-aware functionality and identify post-synthesis issues
Analyze simulation results, debug functional failures, and collaborate with RTL designers to resolve design defects efficiently
Review architecture and design specifications to identify verification requirements and potential corner cases
Verify low-power functionality and ensure compliance with power management requirements across multiple operating modes
Participate in verification reviews, test plan discussions, and regression analysis to improve verification quality and productivity
Work closely with cross-functional teams including RTL Design, Physical Design, DFT, Validation, and Software teams throughout the development lifecycle
Contribute to the continuous enhancement of verification methodologies, automation, and reusable verification IP

Required Skills

Strong experience as a Design Verification Engineer in semiconductor or SoC development
Hands-on expertise in SystemVerilog (SV) and UVM for building scalable verification environments
Solid understanding of Power Management Unit (PMU) architecture and verification methodologies
Good knowledge of basic digital design concepts including sequential and combinational logic, FSMs, clocks, resets, and synchronization
Practical experience in Gate-Level Simulation (GLS) and debugging timing-related issues
Understanding of IESNLP concepts and their application within verification workflows
Experience in writing verification components such as drivers, monitors, scoreboards, sequences, assertions, and checkers
Strong debugging skills using waveform analysis and simulation tools
Familiarity with regression execution, bug tracking, and verification closure
Excellent analytical, problem-solving, and communication skills

Good-to-Have Skills

Scripting knowledge using Python, Perl, Shell, or Tcl to automate verification tasks and regression flows
Good understanding of functional and code coverage analysis for achieving verification closure
Exposure to assertion-based verification and low-power verification methodologies
Familiarity with modem subsystems or complex SoC architectures
Experience working in Agile or collaborative semiconductor development environments

Qualifications

B.Tech/B.E./M.Tech/M.E. in Electronics, Electrical Engineering, Computer Engineering, or a related discipline
4-8 years of relevant experience in semiconductor design verification with strong exposure to PMU verification
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