Design Verification Engineer (PMU Verification - Modem Subsystem)

This role is for one of the Weekday's clients

Min Experience: 4+ years

Location: Bengaluru

JobType: full-time

Requirements

Job Responsibilities:

Perform Design Verification of Power Management Unit (PMU) blocks in the Modem Subsystem
Develop and execute SystemVerilog/UVM-based verification environments, testcases, and regression suites
Create verification plans and ensure functional coverage closure
Debug RTL, testbench, and simulation failures efficiently
Perform Gate-Level Simulations (GLS) and analyze timing-related issues
Verify low-power functionality and power management features
Work closely with RTL designers to resolve design and verification issues
Ensure high-quality verification deliverables while meeting project timelines

Mandatory Skills:

Strong hands-on experience in SystemVerilog (SV) and UVM
Good understanding of Digital Design fundamentals
Experience in Power Management Unit (PMU) verification or Low-Power Verification
Understanding of IESNLP methodology/concepts
Experience with Gate-Level Simulations (GLS)
Knowledge of functional coverage, assertions, and debugging techniques
Good problem-solving and communication skills

Must-have Skills

Power Management Unit, SystemVerilog, Universal Verification Methodology - UVM

Good-to-have Skills

Digital Design fundamentals, Gate-Level Simulations
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