Design Verification Engineer – PCIe/CXL Protocol (5+ Years Experience)

About RTLYNX
RTLYNX is a leading semiconductor engineering services company specializing in VLSI design, verification, embedded systems, and silicon solutions. We work with global semiconductor organizations to deliver high-quality, cutting-edge technology solutions across advanced SoC and ASIC development programs.
Position: Design Verification Engineer – PCIe/CXL Protocol
Location: Bangalore, India
Experience: 5+ Years
Open Positions: 10
Employment Type: Full-Time
Job Summary
We are looking for experienced Design Verification Engineers with strong expertise in PCIe and/or CXL protocol verification. The ideal candidate should possess hands-on experience in SystemVerilog and UVM-based verification environments and have worked on complex SoC/ASIC verification projects within the semiconductor industry.
This role offers an opportunity to work on next-generation high-speed interconnect technologies and contribute to the development of advanced silicon products for global customers.
Key Responsibilities
Develop and execute comprehensive verification plans for PCIe and/or CXL-based IPs and subsystems.
Design, develop, and maintain reusable verification environments using SystemVerilog and UVM methodologies.
Create test plans, test cases, constrained-random tests, assertions, and functional coverage models.
Debug RTL, simulation, and protocol-level issues independently.
Analyze verification results and drive closure of coverage metrics.
Work closely with RTL designers, architects, and validation teams to ensure high-quality silicon.
Review design specifications and identify verification requirements.
Participate in code reviews, verification reviews, and project status discussions.
Develop protocol checkers, scoreboards, monitors, and coverage collectors.
Ensure verification sign-off criteria are achieved within project timelines.
Mandatory SkillsProtocol Expertise
Strong hands-on experience in:
PCIe (Gen3/Gen4/Gen5 preferred)
CXL (Compute Express Link)
Deep understanding of:
LTSSM
Transaction Layer
Data Link Layer
Physical Layer concepts
Flow Control
Error Handling
Protocol Compliance
Verification Skills
Strong expertise in:
SystemVerilog
UVM (Universal Verification Methodology)
Experience with:
Assertions (SVA)
Functional Coverage
Constrained Random Verification
Testbench Architecture Development
Protocol Verification Methodologies
Additional Technical Skills
Experience in SoC/ASIC Verification.
Understanding of industry-standard verification tools.
Strong debugging and problem-solving skills.
Experience working in Linux/Unix environments.
Familiarity with scripting languages such as Python, Perl, Shell, or TCL is an added advantage.
Preferred Qualifications
Bachelor's or Master's degree in Electronics, Electrical Engineering, VLSI, Microelectronics, or related fields.
Experience in semiconductor product companies or VLSI service organizations.
Exposure to VIP integration and protocol compliance testing.
Knowledge of AMBA protocols (AXI/AHB/APB) will be a plus.
Experience working on complex SoC verification environments is desirable.
What We're Looking For
Strong analytical and debugging skills.
Excellent communication and collaboration abilities.
Ability to work independently and drive verification tasks to completion.
Passion for solving challenging verification problems in advanced semiconductor designs.
Why Join RTLYNX?
Opportunity to work on cutting-edge semiconductor technologies.
Exposure to global semiconductor customers and advanced silicon programs.
Collaborative engineering culture.
Career growth in high-performance VLSI and verification domains.
Work alongside experienced industry experts.
Apply Now
If you are passionate about VLSI Design Verification and have strong PCIe/CXL protocol expertise with SystemVerilog/UVM skills, we'd love to hear from you.
📧 Share your updated resume with:
careers@rtlynx.com
🌐 Company Website: www.rtlynx.com
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