QG
Design Verification Engineer ( PCIe )
Accepting applicationsQuest Global · San Jose, CA
Full-Time Mid_senior PCIeRTLSoCSystemVerilogUVM
Posted
1d ago
Category
Verification
Experience
Mid_senior
Country
United States
Job Summary:
We are seeking a highly skilled PCIe Verification Engineer with strong expertise in SystemVerilog and UVM-based verification methodologies. The selected candidate will be responsible for verifying complex PCIe IP/SoC designs, developing robust verification environments, creating test plans, and ensuring first-pass silicon success.
Key Responsibilities
Develop and execute comprehensive verification plans for PCIe Controller.
Build reusable and scalable UVM-based verification environments.
Develop SystemVerilog/UVM testbenches, sequences, scoreboards, monitors, and coverage models.
Verify PCIe protocols from Gen1 through Gen6 (based on project requirements).
Create directed and constrained-random test cases.
Perform protocol compliance verification and interoperability testing.
Analyze simulation results, debug failures, and identify RTL/design issues.
Collaborate closely with architects, RTL designers, and firmware teams.
Drive functional, code, assertion, and toggle coverage closure.
Develop and maintain verification documentation and reports.
Required Technical Skills
Strong experience in SystemVerilog and UVM
Expertise in PCIe protocol verification
Experience with: PCIe Gen3/Gen4/Gen5/Gen
Qualification
Bachelor's or Master's degree in Electronics, VLSI, Electrical Engineering, or related fiel
5+ years of experience in verification Engineerin
At least 2+ years of hands-on PCIe verification experienc
Proven experience developing UVM environments from scratch
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We are seeking a highly skilled PCIe Verification Engineer with strong expertise in SystemVerilog and UVM-based verification methodologies. The selected candidate will be responsible for verifying complex PCIe IP/SoC designs, developing robust verification environments, creating test plans, and ensuring first-pass silicon success.
Key Responsibilities
Develop and execute comprehensive verification plans for PCIe Controller.
Build reusable and scalable UVM-based verification environments.
Develop SystemVerilog/UVM testbenches, sequences, scoreboards, monitors, and coverage models.
Verify PCIe protocols from Gen1 through Gen6 (based on project requirements).
Create directed and constrained-random test cases.
Perform protocol compliance verification and interoperability testing.
Analyze simulation results, debug failures, and identify RTL/design issues.
Collaborate closely with architects, RTL designers, and firmware teams.
Drive functional, code, assertion, and toggle coverage closure.
Develop and maintain verification documentation and reports.
Required Technical Skills
Strong experience in SystemVerilog and UVM
Expertise in PCIe protocol verification
Experience with: PCIe Gen3/Gen4/Gen5/Gen
Qualification
Bachelor's or Master's degree in Electronics, VLSI, Electrical Engineering, or related fiel
5+ years of experience in verification Engineerin
At least 2+ years of hands-on PCIe verification experienc
Proven experience developing UVM environments from scratch
Show more Show less