OG
Design Verification Engineer - GPU
Accepting applicationsOho Group · Santa Clara, CA
Full-Time Mid_senior ASICRTLSoCSystemVerilogUVM
Posted
2d ago
Category
Verification
Experience
Mid_senior
Country
United States
GPU Design Verification needed for a Series A Start-up.
Responsibilities
Develop and execute comprehensive verification plans for GPU/TPU system-level functionality.
Design and implement reusable UVM/SystemVerilog verification environments for GPU subsystems, incorporating runtime RTL-to-reference C model checkers across processing pipeline stages.
Develop assertion-based verification (SystemVerilog Assertions - SVA) and functional coverage models to ensure design correctness.
Debug RTL, verification environments, and software issues using waveform analysis and simulation/debug tools.
Qualifications
BS, MS, or PhD in Computer Engineering, Electrical Engineering, Computer Science, or a related field.
5+ years of ASIC/SoC verification experience (Senior-level role).
Strong proficiency in SystemVerilog and the Universal Verification Methodology (UVM).
Solid understanding of modern CPU, GPU, and SoC architectures.
Hands-on experience with constrained-random verification methodologies.
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Responsibilities
Develop and execute comprehensive verification plans for GPU/TPU system-level functionality.
Design and implement reusable UVM/SystemVerilog verification environments for GPU subsystems, incorporating runtime RTL-to-reference C model checkers across processing pipeline stages.
Develop assertion-based verification (SystemVerilog Assertions - SVA) and functional coverage models to ensure design correctness.
Debug RTL, verification environments, and software issues using waveform analysis and simulation/debug tools.
Qualifications
BS, MS, or PhD in Computer Engineering, Electrical Engineering, Computer Science, or a related field.
5+ years of ASIC/SoC verification experience (Senior-level role).
Strong proficiency in SystemVerilog and the Universal Verification Methodology (UVM).
Solid understanding of modern CPU, GPU, and SoC architectures.
Hands-on experience with constrained-random verification methodologies.
Show more Show less