LD
Design Verification Engineer (GLS)
Accepting applicationsleadIC Design Pvt Ltd · Hyderabad, Telangana, India
Full-Time Mid_senior CMOSRTLSoCSystemVerilogUVM
Posted
2d ago
Category
Verification
Experience
Mid_senior
Country
India
Experience: 3+yrs
Location: Hyd/Blr
Job Overview
We are looking for a Design Verification Engineer with hands-on experience in SystemVerilog/UVM, Verilog, pre-silicon verification and Gate-Level Simulation (GLS) to work on SoC/full-chip DRAM verification.
The ideal candidate should have strong fundamentals in digital/analog circuits and CMOS concepts, along with practical experience in developing and executing verification environments, debugging failures, managing regressions and working with cross-functional teams using industry-standard EDA tools.
Key Responsibilities
Develop and execute pre-silicon verification environments for SoC/full-chip designs with focus on DRAM verification.
Develop and maintain SystemVerilog/UVM-based verification components, testbenches, sequences, tests and checkers.
Work with Verilog/SystemVerilog RTL and understand design behavior at block, subsystem and full-chip levels.
Perform Gate-Level Simulation (GLS) and analyze simulation behavior across different scenarios.
Develop and implement SystemVerilog Assertions (SVA) to verify functional and interface-level requirements.
Execute verification regressions, analyze failures and identify root causes across RTL, testbench, assertions and simulation environments.
Debug functional and simulation issues and work closely with RTL/design teams to drive issues to closure.
Optimize regression environments to improve simulation efficiency, coverage and debug turnaround time.
Use industry-standard EDA verification tools for simulation, debug and regression execution.
Collaborate with design, architecture, verification and other cross-functional teams during the verification cycle.
Contribute to verification planning, test development, coverage analysis and overall SoC/full-chip verification sign-off.
Required Skills
Must-Have
3+ year of hands-on Design Verification experience
Strong knowledge of SystemVerilog and UVM
Good working experience with Verilog
Experience with pre-silicon verification
Hands-on experience with Gate-Level Simulation (GLS)
Good understanding and practical experience with SystemVerilog Assertions
Hands-on experience in debugging simulation failures and verification issues
Experience running and analyzing regressions
Experience with SoC/full-chip verification
Hands-on experience in DRAM verification
Good understanding of digital and analog circuit fundamentals
Good understanding of CMOS concepts
Comfortable working with EDA tools
Strong cross-functional collaboration and communication skills
Preferred Qualifications
B.E./B.Tech in Electronics / Electronics & Communication / Electrical Engineering or M.Tech in a relevant discipline.
Experience with memory subsystem verification.
Experience working on complex SoC/full-chip verification environments.
Exposure to functional coverage, constrained-random verification and verification planning.
Familiarity with simulation/debug environments and common EDA verification flows.
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Location: Hyd/Blr
Job Overview
We are looking for a Design Verification Engineer with hands-on experience in SystemVerilog/UVM, Verilog, pre-silicon verification and Gate-Level Simulation (GLS) to work on SoC/full-chip DRAM verification.
The ideal candidate should have strong fundamentals in digital/analog circuits and CMOS concepts, along with practical experience in developing and executing verification environments, debugging failures, managing regressions and working with cross-functional teams using industry-standard EDA tools.
Key Responsibilities
Develop and execute pre-silicon verification environments for SoC/full-chip designs with focus on DRAM verification.
Develop and maintain SystemVerilog/UVM-based verification components, testbenches, sequences, tests and checkers.
Work with Verilog/SystemVerilog RTL and understand design behavior at block, subsystem and full-chip levels.
Perform Gate-Level Simulation (GLS) and analyze simulation behavior across different scenarios.
Develop and implement SystemVerilog Assertions (SVA) to verify functional and interface-level requirements.
Execute verification regressions, analyze failures and identify root causes across RTL, testbench, assertions and simulation environments.
Debug functional and simulation issues and work closely with RTL/design teams to drive issues to closure.
Optimize regression environments to improve simulation efficiency, coverage and debug turnaround time.
Use industry-standard EDA verification tools for simulation, debug and regression execution.
Collaborate with design, architecture, verification and other cross-functional teams during the verification cycle.
Contribute to verification planning, test development, coverage analysis and overall SoC/full-chip verification sign-off.
Required Skills
Must-Have
3+ year of hands-on Design Verification experience
Strong knowledge of SystemVerilog and UVM
Good working experience with Verilog
Experience with pre-silicon verification
Hands-on experience with Gate-Level Simulation (GLS)
Good understanding and practical experience with SystemVerilog Assertions
Hands-on experience in debugging simulation failures and verification issues
Experience running and analyzing regressions
Experience with SoC/full-chip verification
Hands-on experience in DRAM verification
Good understanding of digital and analog circuit fundamentals
Good understanding of CMOS concepts
Comfortable working with EDA tools
Strong cross-functional collaboration and communication skills
Preferred Qualifications
B.E./B.Tech in Electronics / Electronics & Communication / Electrical Engineering or M.Tech in a relevant discipline.
Experience with memory subsystem verification.
Experience working on complex SoC/full-chip verification environments.
Exposure to functional coverage, constrained-random verification and verification planning.
Familiarity with simulation/debug environments and common EDA verification flows.
Show more Show less