A
Design Verification Engineer (DDR)_5+ Years_ Bangalore/Hyderabad
Accepting applicationsAIonSi · Bengaluru South, Karnataka, India
Full-Time Entry AIASICDDRPerlPython
Estimated market salary
₹10-17 LPA
This is a SiliconBoard market estimate, not an employer-posted salary.
Posted
4d ago
Category
Verification
Experience
Entry
Country
India
Company Description AIonSi is a semiconductor solutions startup delivering VLSI design and verification, automotive functional safety, and AI-based services to global semiconductor clients. Led by seven industry experts, the company specializes in end-to-end solutions for complex SoC designs, taking complete ownership from concept to implementation. AIonSi operates as a one-stop platform, emphasizing best-in-class service without compromising on quality. The organization offers comprehensive expertise across IP and SoC design, integration, verification, gate-level simulation (GLS), and physical design, providing a strong technical environment for engineering professionals.
Role Description This is a full-time, on-site Design Verification Engineer (DDR) role based in Bengaluru South. The engineer will focus on DDR subsystem and interface verification, developing and executing verification plans, testbenches, and test cases to ensure functional correctness and performance compliance. Day-to-day responsibilities include writing and reviewing RTL and verification code, building and maintaining verification environments, running simulations, and analyzing coverage to close gaps. The role involves debugging complex issues at block and subsystem levels, collaborating closely with design, architecture, and validation teams, and documenting verification methodologies and results. The engineer will also contribute to process improvements, best practices, and technical reviews across projects.
Qualifications
Strong skills in Functional Verification and Debugging to validate DDR and SoC-level designs and resolve complex design and testbench issues.
Proficiency in Formal Verification techniques to complement simulation-based verification and improve coverage and quality.
Solid understanding of RTL Design principles for digital logic, with the ability to review and interpret RTL implementations for verification.
Good knowledge of Computer Architecture, memory subsystems, and DDR protocols to ensure accurate and efficient verification strategies.
5+ years of hands-on experience in ASIC/SoC verification, preferably with focus on DDR or high-speed memory interfaces.
Experience with industry-standard verification methodologies and tools (e.g., SystemVerilog, UVM, simulation and formal tools from major EDA vendors).
Familiarity with version control, scripting (such as Python, Perl, or Shell), and automation for efficient verification flows.
Bachelor’s or Master’s degree in Electrical Engineering, Electronics, Computer Engineering, or a related discipline.
Effective communication skills and ability to collaborate with cross-functional teams in a fast-paced engineering environment.
Experience : 5+ years
Location : Bangalore
Preference : Immediate Joiners
Show more Show less
Role Description This is a full-time, on-site Design Verification Engineer (DDR) role based in Bengaluru South. The engineer will focus on DDR subsystem and interface verification, developing and executing verification plans, testbenches, and test cases to ensure functional correctness and performance compliance. Day-to-day responsibilities include writing and reviewing RTL and verification code, building and maintaining verification environments, running simulations, and analyzing coverage to close gaps. The role involves debugging complex issues at block and subsystem levels, collaborating closely with design, architecture, and validation teams, and documenting verification methodologies and results. The engineer will also contribute to process improvements, best practices, and technical reviews across projects.
Qualifications
Strong skills in Functional Verification and Debugging to validate DDR and SoC-level designs and resolve complex design and testbench issues.
Proficiency in Formal Verification techniques to complement simulation-based verification and improve coverage and quality.
Solid understanding of RTL Design principles for digital logic, with the ability to review and interpret RTL implementations for verification.
Good knowledge of Computer Architecture, memory subsystems, and DDR protocols to ensure accurate and efficient verification strategies.
5+ years of hands-on experience in ASIC/SoC verification, preferably with focus on DDR or high-speed memory interfaces.
Experience with industry-standard verification methodologies and tools (e.g., SystemVerilog, UVM, simulation and formal tools from major EDA vendors).
Familiarity with version control, scripting (such as Python, Perl, or Shell), and automation for efficient verification flows.
Bachelor’s or Master’s degree in Electrical Engineering, Electronics, Computer Engineering, or a related discipline.
Effective communication skills and ability to collaborate with cross-functional teams in a fast-paced engineering environment.
Experience : 5+ years
Location : Bangalore
Preference : Immediate Joiners
Show more Show less