C
Design Verification Engineer – CPU Core
Accepting applicationsChiparama · San Jose, CA
Contract Mid_senior MIPSPerlPythonRISC-VRTL
Posted
10 Jun
Category
Design
Experience
Mid_senior
Country
United States
Design Verification Engineer – CPU Core & Subsystems (Remote)
Chiparama is hiring experienced DV engineers — on behalf of a leading CPU IP company — to own verification and debug of a next-generation CPU core and its surrounding subsystems, with a focus on the integer core and load-store unit (LSU).
What you'll do
Triage and root-cause RTL and DV bugs across a CPU core and surrounding subsystems
Drive verification of the integer core and load-store units — pipelines, hazards, ordering, memory coherency
Build and extend SystemVerilog/UVM testbench components, sequences, and checkers
Write SystemVerilog Assertions (SVA) and close functional coverage on targeted features
Separate RTL bugs from testbench issues and route them with clear, reproducible findings
What you bring
5–15 years of CPU/SoC design verification experience
Proven ability to triage and root-cause RTL and DV bugs in a CPU and its subsystems
Strong CPU microarchitecture knowledge — integer execution and load-store behavior
Proficiency in SystemVerilog and UVM; sharp waveform/log debug discipline
Nice to have
Assertions (SVA), functional coverage, and testbench development depth
RISC-V or MIPS familiarity; scripting (Python/Perl/Tcl) for regression automation
Show more Show less
Chiparama is hiring experienced DV engineers — on behalf of a leading CPU IP company — to own verification and debug of a next-generation CPU core and its surrounding subsystems, with a focus on the integer core and load-store unit (LSU).
What you'll do
Triage and root-cause RTL and DV bugs across a CPU core and surrounding subsystems
Drive verification of the integer core and load-store units — pipelines, hazards, ordering, memory coherency
Build and extend SystemVerilog/UVM testbench components, sequences, and checkers
Write SystemVerilog Assertions (SVA) and close functional coverage on targeted features
Separate RTL bugs from testbench issues and route them with clear, reproducible findings
What you bring
5–15 years of CPU/SoC design verification experience
Proven ability to triage and root-cause RTL and DV bugs in a CPU and its subsystems
Strong CPU microarchitecture knowledge — integer execution and load-store behavior
Proficiency in SystemVerilog and UVM; sharp waveform/log debug discipline
Nice to have
Assertions (SVA), functional coverage, and testbench development depth
RISC-V or MIPS familiarity; scripting (Python/Perl/Tcl) for regression automation
Show more Show less
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