VT
Design Verification Engineer
Accepting applicationsVings Technologies · San Jose, CA
Full-Time Mid RTLSoCUVMVerilog
Posted
3d ago
Category
Verification
Experience
Mid
Country
United States
Role: Design Verification Engineer
Location: San Jose, CA - Onsite
Experience: 8+ years
Mandatory Skills: HBM2E/HBM3/HBM3E hands-on verification; SV/UVM; memory controller/subsystem DV; coverage & debug
Job Description
Role Summary
We are seeking DV engineers to verify complex internal IP blocks such as compute engines, accelerators, and custom logic within SoC environments.
Key Responsibilities
Develop and maintain UVM-based verification environments
Create test plans, testcases, and coverage models
Perform functional verification of RTL designs
Debug RTL and testbench issues
Drive coverage closure (functional + code)
Required Skills
Strong hands-on with System Verilog and UVM
Experience in block-level verification
Good understanding of digital design fundamentals
Experience with debug tools (Verdi, DVE, etc.)
Good To Have
Exposure to low-power verification (UPF)
Experience with AMBA protocols (AXI/AHB/APB)
Show more Show less
Location: San Jose, CA - Onsite
Experience: 8+ years
Mandatory Skills: HBM2E/HBM3/HBM3E hands-on verification; SV/UVM; memory controller/subsystem DV; coverage & debug
Job Description
Role Summary
We are seeking DV engineers to verify complex internal IP blocks such as compute engines, accelerators, and custom logic within SoC environments.
Key Responsibilities
Develop and maintain UVM-based verification environments
Create test plans, testcases, and coverage models
Perform functional verification of RTL designs
Debug RTL and testbench issues
Drive coverage closure (functional + code)
Required Skills
Strong hands-on with System Verilog and UVM
Experience in block-level verification
Good understanding of digital design fundamentals
Experience with debug tools (Verdi, DVE, etc.)
Good To Have
Exposure to low-power verification (UPF)
Experience with AMBA protocols (AXI/AHB/APB)
Show more Show less