SI
Design Verification Engineer
Accepting applicationsSysTechCorp Inc · Texas, United States
Full-Time Mid_senior CadenceMentorPerlRTLSystemVerilog
Posted
2d ago
Category
Verification
Experience
Mid_senior
Country
United States
Hello All,
Hope you're doing well. We have an urgent opening for the following,
Role : Design Verification Enginee
rLocation : Austin TX/Boston MA/Bay Area CA onsit
eExp: 5 to 18 yr
s
VisaType : H4EAD, USC and GC On
ly
For these roles, we’re particularly interested in engineers with strong expertise in SystemVerilog and UVM, a proven track record of formal verification ownership, and a solid understanding of RTL. Additionally, exposure to fabric/interconnect or architecture-level designs would be a significant pl
us.
Data Fabric verification engineer: 5 to 20 years of experi
ence
PREFERRED EXPERI
ENCE:Architected and developed complex verification environments in SystemVerilog, including scripting using Perl, Ruby, Make, or the l
ikes.Exposure to RTL design, software development, formal verification, or other related dom
ains.Good understanding of computer organization/architec
ture.Experience or familiarity with formal tools and/or functional verification tools by VCS, Cadence, Mentor Gra
phics
KEY RESPONSIBL
ITIES:Write tests, sequences, and testbench components in SystemVerilog and UVM along with formal to achieve verification of the d
esign.Coordinate with RTL engineers to implement logic design for better clock gating and verify the various aspects of the d
esign.Interact with architects, RTL designers, performance engineers, and post-silicon validation engineers to develop deep expertise in the Infinity Fabric archite
cture.Collaborate with architects, hardware engineers and multiple IP development g
roups.Drive formal verification for the block and write formal properties and assertions to verify the
designResponsible for verification quality metrics like pass rates, code coverage and functional co
verage
ACADEMIC CRED
ENTIALS:Bachelors or Masters degree in computer engineering/Electrical Engineering p
referred
Show more Show less
Hope you're doing well. We have an urgent opening for the following,
Role : Design Verification Enginee
rLocation : Austin TX/Boston MA/Bay Area CA onsit
eExp: 5 to 18 yr
s
VisaType : H4EAD, USC and GC On
ly
For these roles, we’re particularly interested in engineers with strong expertise in SystemVerilog and UVM, a proven track record of formal verification ownership, and a solid understanding of RTL. Additionally, exposure to fabric/interconnect or architecture-level designs would be a significant pl
us.
Data Fabric verification engineer: 5 to 20 years of experi
ence
PREFERRED EXPERI
ENCE:Architected and developed complex verification environments in SystemVerilog, including scripting using Perl, Ruby, Make, or the l
ikes.Exposure to RTL design, software development, formal verification, or other related dom
ains.Good understanding of computer organization/architec
ture.Experience or familiarity with formal tools and/or functional verification tools by VCS, Cadence, Mentor Gra
phics
KEY RESPONSIBL
ITIES:Write tests, sequences, and testbench components in SystemVerilog and UVM along with formal to achieve verification of the d
esign.Coordinate with RTL engineers to implement logic design for better clock gating and verify the various aspects of the d
esign.Interact with architects, RTL designers, performance engineers, and post-silicon validation engineers to develop deep expertise in the Infinity Fabric archite
cture.Collaborate with architects, hardware engineers and multiple IP development g
roups.Drive formal verification for the block and write formal properties and assertions to verify the
designResponsible for verification quality metrics like pass rates, code coverage and functional co
verage
ACADEMIC CRED
ENTIALS:Bachelors or Masters degree in computer engineering/Electrical Engineering p
referred
Show more Show less