SI
Design Verification Engineer
Accepting applicationsSysTechCorp Inc · Austin, Texas Metropolitan Area
Full-Time Mid_senior CadenceMentorPerlRTLSystemVerilog
Posted
2d ago
Category
Verification
Experience
Mid_senior
Country
United States
Hello,
Hope you’re doing well. We have an urgent opening for
Role :Design Verification Engineer
Location : Austin TX/Boston MA/Bay Area CA onsite
For these roles, we’re particularly interested in engineers with strong expertise in SystemVerilog and UVM, a proven track record of formal verification ownership, and a solid understanding of RTL. Additionally, exposure to fabric/interconnect or architecture-level designs would be a significant plus.
Data Fabric verification engineer: 5 to 20 years of experience
PREFERRED EXPERIENCE:
Architected and developed complex verification environments in SystemVerilog, including scripting using Perl, Ruby, Make, or the likes.
Exposure to RTL design, software development, formal verification, or other related domains.
Good understanding of computer organization/architecture.
Experience or familiarity with formal tools and/or functional verification tools by VCS, Cadence, Mentor Graphics
KEY RESPONSIBLITIES:
Write tests, sequences, and testbench components in SystemVerilog and UVM along with formal to achieve verification of the design.
Coordinate with RTL engineers to implement logic design for better clock gating and verify the various aspects of the design.
Interact with architects, RTL designers, performance engineers, and post-silicon validation engineers to develop deep expertise in the Infinity Fabric architecture.
Collaborate with architects, hardware engineers and multiple IP development groups.
Drive formal verification for the block and write formal properties and assertions to verify the design
Responsible for verification quality metrics like pass rates, code coverage and functional coverage
Show more Show less
Hope you’re doing well. We have an urgent opening for
Role :Design Verification Engineer
Location : Austin TX/Boston MA/Bay Area CA onsite
For these roles, we’re particularly interested in engineers with strong expertise in SystemVerilog and UVM, a proven track record of formal verification ownership, and a solid understanding of RTL. Additionally, exposure to fabric/interconnect or architecture-level designs would be a significant plus.
Data Fabric verification engineer: 5 to 20 years of experience
PREFERRED EXPERIENCE:
Architected and developed complex verification environments in SystemVerilog, including scripting using Perl, Ruby, Make, or the likes.
Exposure to RTL design, software development, formal verification, or other related domains.
Good understanding of computer organization/architecture.
Experience or familiarity with formal tools and/or functional verification tools by VCS, Cadence, Mentor Graphics
KEY RESPONSIBLITIES:
Write tests, sequences, and testbench components in SystemVerilog and UVM along with formal to achieve verification of the design.
Coordinate with RTL engineers to implement logic design for better clock gating and verify the various aspects of the design.
Interact with architects, RTL designers, performance engineers, and post-silicon validation engineers to develop deep expertise in the Infinity Fabric architecture.
Collaborate with architects, hardware engineers and multiple IP development groups.
Drive formal verification for the block and write formal properties and assertions to verify the design
Responsible for verification quality metrics like pass rates, code coverage and functional coverage
Show more Show less