Design Verification Engineer

Seeking a skilled Design Verification Engineer with strong expertise in System Verilog (SV) and UVM methodologies. The ideal candidate will have hands-on experience developing, updating, and debugging verification testbenches, with the ability to integrate Verification IPs (VIPs) or Design IPs into the verification environment.

Responsibilities

Develop, enhance, and debug System Verilog/UVM-based testbenches for complex designs.

Integrate VIP/IP components and ensure smooth functionality within the verification environment.

Mentor team members and support cross-functional verification activities.

Collaborate with design engineers to understand specifications and create robust verification plans.

Perform simulation, debug failures, and implement fixes effectively.

Required Skills

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.

Strong proficiency in System Verilog and UVM.

Hands-on experience updating and debugging verification testbenches.

Excellent problem-solving and analytical skills.

Strong verbal and written communication skills for effective team collaboration.

Preferred Skills

Experience with C-based testbenches.

Experience integrating VIP/IPs.

Proficiency in scripting languages such as Perl, Python, or TCL for automation.

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