SS
Design Verification Engineer
Accepting applicationsSmartSoC Solutions Pvt Ltd · Greater Bengaluru Area
Full-Time Mid_senior PCIeUVM
Posted
1d ago
Category
Verification
Experience
Mid_senior
Country
India
Location: Bangalore
Experience: 5+yrs
PCIe Gen5/Gen6: Knowledge of high-speed PCIe architecture, link training, LTSSM, speed/width negotiation, resets, and error handling.
TL (Transaction Layer): Verify TLPs, Memory/Config transactions, completions, ordering, tags, and flow control.
DL (Data Link Layer): Verify DLLPs, ACK/NAK, sequence numbers, replay, CRC/LCRC, and error recovery.
PHY: Verify LTSSM, lane training, link width/speed, equalization, and recovery.
UVM from scratch: Build the environment including agents, drivers, monitors, sequencers, scoreboard, assertions, coverage, tests, and regression.
Debug: Analyze failures using waveforms, protocol logs, and UVM reports.
Experience working with either connectivity protocols or high speed protocols.
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Experience: 5+yrs
PCIe Gen5/Gen6: Knowledge of high-speed PCIe architecture, link training, LTSSM, speed/width negotiation, resets, and error handling.
TL (Transaction Layer): Verify TLPs, Memory/Config transactions, completions, ordering, tags, and flow control.
DL (Data Link Layer): Verify DLLPs, ACK/NAK, sequence numbers, replay, CRC/LCRC, and error recovery.
PHY: Verify LTSSM, lane training, link width/speed, equalization, and recovery.
UVM from scratch: Build the environment including agents, drivers, monitors, sequencers, scoreboard, assertions, coverage, tests, and regression.
Debug: Analyze failures using waveforms, protocol logs, and UVM reports.
Experience working with either connectivity protocols or high speed protocols.
Show more Show less