SI
Design Verification Engineer
Accepting applicationsSintegra Inc. · Sunnyvale, CA
Full-Time Mid_senior EthernetPCIeSoCSystemVerilogUVM
Posted
28 May
Category
Verification
Experience
Mid_senior
Country
United States
Role Overview
We are looking for a Design Verification Engineer to support SoC-level verification of advanced high-speed and security IP. This role involves close collaboration with design and architecture teams to verify complex digital systems.
Responsibilities
Develop and execute SoC and IP-level verification using SystemVerilog and UVM
Verify UCIe, Ethernet MAC & PCS, and PCIe designs
Support PCIe Root of Trust verification, including Rambus IP
Create verification plans, tests, assertions, and coverage
Debug issues and drive verification closure
Requirements
BS/MS in EE, CE, or related field
5+ years of SoC Design Verification experience
Strong SystemVerilog / UVM skills
Show more Show less
We are looking for a Design Verification Engineer to support SoC-level verification of advanced high-speed and security IP. This role involves close collaboration with design and architecture teams to verify complex digital systems.
Responsibilities
Develop and execute SoC and IP-level verification using SystemVerilog and UVM
Verify UCIe, Ethernet MAC & PCS, and PCIe designs
Support PCIe Root of Trust verification, including Rambus IP
Create verification plans, tests, assertions, and coverage
Debug issues and drive verification closure
Requirements
BS/MS in EE, CE, or related field
5+ years of SoC Design Verification experience
Strong SystemVerilog / UVM skills
Show more Show less