SE
Design Verification Engineer
Accepting applicationsSaur Energy International · Location, WV
Full-Time Mid C++PerlPythonRTLSoC
Posted
20h ago
Category
Verification
Experience
Mid
Country
United States
Overview
Microsoft is a highly innovative company that collaborates across disciplines to produce cutting edge technology that changes our world. Microsoft’s Silicon team builds custom silicon for a diverse set of systems ranging from innovative consumer products like Xbox to high-performance Azure cloud servers, clients, and augmented reality.
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We are looking for a design verification engineer to work in the dynamic Microsoft Artificial Intelligence Silicon Engineering (AISiE) team. The candidate should be a highly motivated self-starter who will thrive in this cutting-edge technical environment.
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Microsoft’s mission is to empower every person and every organization on the planet to achieve more. As employees we come together with a growth mindset, innovate to empower others, and collaborate to realize our shared goals. Each day we build on our values of respect, integrity, and accountability to create a culture of inclusion where everyone can thrive at work and beyond.
Responsibilities
The AISiE silicon team is seeking a passionate, driven, and intellectually curious computer/electrical engineer to deliver premium-quality designs once considered impossible. We are responsible for delivering cutting-edge, custom IP and SoC designs that can perform complex and high-performance functions in an extremely efficient manner.
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Plan the verification of complex design IP/SoC interacting with the architecture and design engineers to identify verification test scenarios.
Create and enhance constrained-random verification environments using SystemVerilog and UVM, or formally verify designs with SVA and industry leading formal tools
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Develop tests using UVM or C/C++
Analyse and debug test failures with designers to deliver functionally correct design.
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Identify and write functional coverage for stimulus and corner cases.
Close coverage to plug verification holes and meet tape out requirements.
Qualifications
3 or more years of experience in design verification with a proven track record of delivering complex CPU or SoC IP’s
knowledge of verification principles, testbenches, stimulus generation, and UVM or C++ based test environments.
good understanding of computer architecture
Substantial background in debugging RTL (Verilog) designs as well as simulation and/or emulation environments
Scripting language such as Python or Perl
Show more Show less
Microsoft is a highly innovative company that collaborates across disciplines to produce cutting edge technology that changes our world. Microsoft’s Silicon team builds custom silicon for a diverse set of systems ranging from innovative consumer products like Xbox to high-performance Azure cloud servers, clients, and augmented reality.
Advertisment
We are looking for a design verification engineer to work in the dynamic Microsoft Artificial Intelligence Silicon Engineering (AISiE) team. The candidate should be a highly motivated self-starter who will thrive in this cutting-edge technical environment.
Advertisment
Microsoft’s mission is to empower every person and every organization on the planet to achieve more. As employees we come together with a growth mindset, innovate to empower others, and collaborate to realize our shared goals. Each day we build on our values of respect, integrity, and accountability to create a culture of inclusion where everyone can thrive at work and beyond.
Responsibilities
The AISiE silicon team is seeking a passionate, driven, and intellectually curious computer/electrical engineer to deliver premium-quality designs once considered impossible. We are responsible for delivering cutting-edge, custom IP and SoC designs that can perform complex and high-performance functions in an extremely efficient manner.
Advertisment
Plan the verification of complex design IP/SoC interacting with the architecture and design engineers to identify verification test scenarios.
Create and enhance constrained-random verification environments using SystemVerilog and UVM, or formally verify designs with SVA and industry leading formal tools
Advertisment
Develop tests using UVM or C/C++
Analyse and debug test failures with designers to deliver functionally correct design.
Advertisment
Identify and write functional coverage for stimulus and corner cases.
Close coverage to plug verification holes and meet tape out requirements.
Qualifications
3 or more years of experience in design verification with a proven track record of delivering complex CPU or SoC IP’s
knowledge of verification principles, testbenches, stimulus generation, and UVM or C++ based test environments.
good understanding of computer architecture
Substantial background in debugging RTL (Verilog) designs as well as simulation and/or emulation environments
Scripting language such as Python or Perl
Show more Show less