Design Verification Engineer

Principal / Lead SoC Hardware Engineer – PCIe & Memory Subsystems
Location: San Jose, CA
Experience: 8–10+ Years
Level: Principal / Lead Engineer
Duration: Long Term
Openings: Multiple
Job Summary
We are seeking experienced Principal / Lead SoC Hardware Engineers to support next-generation PCIe Gen5/Gen6 and Memory Controller subsystems for advanced SoC and chiplet-based products.
The positions span RTL Design, Design Verification, Subsystem Integration, Protocol Verification, Memory Controller Design and Verification.
The ideal candidate will have deep expertise in one or more of the following areas:
PCIe Gen5/Gen6 Controller, PHY and SerDes
PCIe Transaction/Data Link/Physical Layers
LTSSM and PIPE
Memory Controllers
ARM CHI/CHI-G
DFI
DDR4/DDR5/LPDDR/HBM
SystemVerilog/UVM
ASIC/SoC subsystem design and verification
Candidates should be comfortable working across the ASIC development lifecycle from architecture/specification through RTL, verification, tape-out, silicon bring-up and post-silicon debug.
Key Responsibilities
PCIe Gen5/Gen6
Lead development, verification and/or integration of PCIe Gen5/Gen6 Controller, PHY and SerDes subsystems.
Work across Transaction, Data Link and Physical layers.
Support LTSSM, PIPE, link training, equalization, recovery, speed changes and lane-width changes.
Support Controller-to-PHY integration and protocol compliance.
Work with PCIe/SerDes/PHY and analog teams to debug subsystem issues.
Support PCIe/CXL interoperability and advanced PCIe features where applicable.
Analyze simulation, emulation, FPGA and post-silicon issues.
Memory Controller / CHI-G / DFI
Lead design and/or verification of DDR/LPDDR/HBM memory controller subsystems.
Work with ARM CHI/CHI-G coherency protocols.
Develop or verify request, response and snoop channel logic.
Work with DFI PHY-facing interfaces and timing/command protocols.
Support command scheduling, arbitration, QoS and bank/rank management.
Verify DFI timing, handshakes and calibration sequences.
Debug memory-controller behavior, coherency and interface timing issues.
Verification
Develop overall verification strategy and test plans.
Architect and develop UVM-based verification environments.
Develop testbenches, scoreboards, checkers, assertions and functional coverage.
Drive functional, code, assertion and cross-coverage closure.
Support formal verification for protocol-critical paths.
Manage regressions, failure triage and bug closure.
Drive verification signoff through tape-out.
Support subsystem and SoC-level verification.
RTL / Design / Integration
Develop and modify SystemVerilog/Verilog RTL.
Extend existing large RTL codebases to support new architectural requirements.
Define subsystem architecture and microarchitecture.
Develop interface specifications and design documentation.
Support synthesis, SDC, STA and timing closure.
Collaborate with Physical Design teams to achieve PPA targets.
Support DFT requirements including Scan, MBIST, LBIST and JTAG/Boundary Scan.
Silicon Bring-Up & Debug
Support pre-silicon simulation, emulation and FPGA prototyping.
Debug silicon issues during bring-up.
Analyze PCIe protocol traces and lab debug logs.
Support PCIe link training and compliance testing.
Correlate pre-silicon verification with post-silicon validation.
Support performance tuning and silicon characterization.
Leadership
Lead and mentor design and/or verification engineers.
Review RTL, verification environments, test plans and coverage.
Drive schedules, milestones and technical execution.
Participate in architecture and design reviews.
Own verification/design signoff activities.
Collaborate with Architecture, RTL, DV, DFT, Physical Design, STA, Firmware and Silicon Validation teams.
Required Qualifications
Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, Computer Engineering or related field.
8–10+ years of ASIC/SoC experience, depending on level.
Strong SystemVerilog/Verilog experience.
Strong understanding of SoC architecture and subsystem integration.
Deep expertise in at least one of the following domains:
PCIe Track
PCIe Gen5/Gen6
PCIe Controller
PHY/SerDes
Transaction/Data Link/Physical Layers
LTSSM
PIPE
Link training/equalization
OR
Memory Controller Track
Memory Controller
DDR4/DDR5/LPDDR/HBM
ARM CHI/CHI-G
DFI
Coherency protocols
For Verification candidates
Strong UVM experience.
Coverage-driven verification.
Assertions/SystemVerilog Assertions.
Formal verification exposure.
Verification planning and signoff.
Leadership of verification teams.
For Design candidates
Strong RTL design experience.
Architecture/microarchitecture experience.
Subsystem integration.
Synthesis/STA/timing closure.
Debugging complex RTL.
Pre- and post-silicon experience.

Regards
Rohit
737 304 7465
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