P
Design Verification Engineer
Accepting applicationsProxelera · Greater Bengaluru Area
Full-Time Mid_senior ASICEthernetPCIEPCIePython
Posted
2d ago
Category
Verification
Experience
Mid_senior
Country
India
Join Proxelera- Innovate the future of VLSI 🌟
If you're looking for a place where you can innovate freely, grow fast, and contribute to something future-facing — Proxelera might just be your next big move.
Job Title: DV Engineers (Ethernet and PCIE)
Work Location: Bangalore (WFO 5 days)
Experience: 5+yrs
Job description:
We are looking for individuals with experience in Design Verification to build IP and System On Chip (SoC) for data center applications. As a Design Verification Engineer, you will be part of a dynamic team working with the best in the industry, focused on developing innovative ASIC solutions for data center applications.
You will be responsible for the verification closure of a design module or sub-system from test-planning, UVM based testbench development to verification closure.
Networking Responsibilities: Define and implement IP/SoC verification plans, build verification test benches to enable IP/sub-system/SoC level verification Develop functional tests based on verification test plan.
Hands-on experience in Verilog, SystemVerilog, UVM , C/C, Python based verification Experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM/OVM based methodologies
Experience in one or more of the following areas along with functional verification - RDMA, PCIe, SRIO & Ethernet, 400G Mac, RDMA, TSO, LRO, PSP,ROCE (RDMA over converged Ethernet), Congestion Control etc
Experience in development of UVM based verification environments from scratch
Show more Show less
If you're looking for a place where you can innovate freely, grow fast, and contribute to something future-facing — Proxelera might just be your next big move.
Job Title: DV Engineers (Ethernet and PCIE)
Work Location: Bangalore (WFO 5 days)
Experience: 5+yrs
Job description:
We are looking for individuals with experience in Design Verification to build IP and System On Chip (SoC) for data center applications. As a Design Verification Engineer, you will be part of a dynamic team working with the best in the industry, focused on developing innovative ASIC solutions for data center applications.
You will be responsible for the verification closure of a design module or sub-system from test-planning, UVM based testbench development to verification closure.
Networking Responsibilities: Define and implement IP/SoC verification plans, build verification test benches to enable IP/sub-system/SoC level verification Develop functional tests based on verification test plan.
Hands-on experience in Verilog, SystemVerilog, UVM , C/C, Python based verification Experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM/OVM based methodologies
Experience in one or more of the following areas along with functional verification - RDMA, PCIe, SRIO & Ethernet, 400G Mac, RDMA, TSO, LRO, PSP,ROCE (RDMA over converged Ethernet), Congestion Control etc
Experience in development of UVM based verification environments from scratch
Show more Show less