P
Design Verification Engineer
Accepting applicationsProgrammers.io · Austin, TX
Full-Time Mid_senior AIDFTRTLSoCUVM
Posted
2d ago
Category
Design
Experience
Mid_senior
Country
United States
Location – Bay Area CA or Austin TX
Title – Design Verification Engineer -AI
This is Fulltime/Permanent rol
e
We need a DV engineer for AMD who has AI experienc
e.The ideal candidate for our AI-based HW IP / SoC development SPW woul
d:Have a good understanding of AI-based HW IP / SoC developmen
t.Be on the forefront of general AI trends (e.g., understanding of various LLMs and their relative strengths/weaknesses based on application
).Have a baseline understanding of DV, including key measurements (e.g., coverage metrics
).
Key Responsibiliti
es:Strong understanding of SV and UVM and good debugging skil
ls.Understanding of AMBA protoco
ls.Understand design specs and develop test plans based on functional and architectural requireme
ntsBuild UVM/System Verilog-based verification environments for IP/subsystem/SoC level test
ingDevelop directed and random testcases, perform coverage analysis, and close functional/code cover
ageDebug simulation failures and work closely with RTL designers to resolve iss
uesExecute regression runs, analyze results, and contribute to continuous improveme
ntsIntegrate and run power-aware simulations, low power checks, and work with UPF/CPF as nee
dedCollaborate with DFT/PD/RTL teams and post-silicon validation to ensure design quality across doma
insDocument test environments, testplans, and results for internal and external revi
ews
Show more Show less
Title – Design Verification Engineer -AI
This is Fulltime/Permanent rol
e
We need a DV engineer for AMD who has AI experienc
e.The ideal candidate for our AI-based HW IP / SoC development SPW woul
d:Have a good understanding of AI-based HW IP / SoC developmen
t.Be on the forefront of general AI trends (e.g., understanding of various LLMs and their relative strengths/weaknesses based on application
).Have a baseline understanding of DV, including key measurements (e.g., coverage metrics
).
Key Responsibiliti
es:Strong understanding of SV and UVM and good debugging skil
ls.Understanding of AMBA protoco
ls.Understand design specs and develop test plans based on functional and architectural requireme
ntsBuild UVM/System Verilog-based verification environments for IP/subsystem/SoC level test
ingDevelop directed and random testcases, perform coverage analysis, and close functional/code cover
ageDebug simulation failures and work closely with RTL designers to resolve iss
uesExecute regression runs, analyze results, and contribute to continuous improveme
ntsIntegrate and run power-aware simulations, low power checks, and work with UPF/CPF as nee
dedCollaborate with DFT/PD/RTL teams and post-silicon validation to ensure design quality across doma
insDocument test environments, testplans, and results for internal and external revi
ews
Show more Show less