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Design Verification Engineer
Accepting applicationsProgrammers.io · United States
Full-Time Mid_senior ASICDFTSoCSystemVerilogUVM
Posted
2d ago
Category
Verification
Experience
Mid_senior
Country
United States
Job Summary
We are seeking a highly motivated Design Verification Engineer to join our semiconductor engineering team. The ideal candidate will be responsible for verifying complex digital IPs, ASICs, and SoCs to ensure functionality, performance, and quality requirements are met before silicon tape-out. The candidate should have strong expertise in verification methodologies, SystemVerilog, UVM, and debugging complex digital designs.
Key Responsibilities
Develop and execute verification plans based on design specifications.
Create reusable verification environments using SystemVerilog and UVM methodology.
Develop testbenches, test cases, checkers, monitors, assertions, and coverage models.
Perform functional, code, and assertion coverage analysis to ensure verification completeness.
Work closely with design engineers to understand architecture and identify verification requirements.
Execute simulations, debug failures, and root-cause design or verification issues.
Develop directed and constrained-random test scenarios.
Analyze waveform data and simulation results using industry-standard EDA tools.
Participate in design reviews, verification reviews, and project planning activities.
Collaborate with cross-functional teams including Design, DFT, Physical Design, and Validation teams.
Support regression runs and continuous integration for verification environments.
Required Qualifications
Bachelor's or Master's degree in Electronics Engineering, Electrical Engineering, Computer Engineering, or related field.
3+ years of experience in Digital Design Verification (experience requirement can be adjusted based on level).
Strong understanding of digital design fundamentals and computer architecture.
Hands-on experience with:
SystemVerilog
UVM (Universal Verification Methodology)
Verilog/VHDL
Assertions (SVA)
Experience in developing constrained-random verification environments.
Knowledge of ASIC/SoC verification flow.
Experience with coverage-driven verification methodologies.
Strong debugging and problem-solving skills.
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We are seeking a highly motivated Design Verification Engineer to join our semiconductor engineering team. The ideal candidate will be responsible for verifying complex digital IPs, ASICs, and SoCs to ensure functionality, performance, and quality requirements are met before silicon tape-out. The candidate should have strong expertise in verification methodologies, SystemVerilog, UVM, and debugging complex digital designs.
Key Responsibilities
Develop and execute verification plans based on design specifications.
Create reusable verification environments using SystemVerilog and UVM methodology.
Develop testbenches, test cases, checkers, monitors, assertions, and coverage models.
Perform functional, code, and assertion coverage analysis to ensure verification completeness.
Work closely with design engineers to understand architecture and identify verification requirements.
Execute simulations, debug failures, and root-cause design or verification issues.
Develop directed and constrained-random test scenarios.
Analyze waveform data and simulation results using industry-standard EDA tools.
Participate in design reviews, verification reviews, and project planning activities.
Collaborate with cross-functional teams including Design, DFT, Physical Design, and Validation teams.
Support regression runs and continuous integration for verification environments.
Required Qualifications
Bachelor's or Master's degree in Electronics Engineering, Electrical Engineering, Computer Engineering, or related field.
3+ years of experience in Digital Design Verification (experience requirement can be adjusted based on level).
Strong understanding of digital design fundamentals and computer architecture.
Hands-on experience with:
SystemVerilog
UVM (Universal Verification Methodology)
Verilog/VHDL
Assertions (SVA)
Experience in developing constrained-random verification environments.
Knowledge of ASIC/SoC verification flow.
Experience with coverage-driven verification methodologies.
Strong debugging and problem-solving skills.
Show more Show less