Design Verification Engineer

Job Title: Design Verification Engineer
Location: Santa Clara, CA (Onsite)
Duration: 12-Month Contract
Employment Type: W2 Contract

Position Overview:
We are seeking highly experienced SoC Design Verification (DV) Engineers to join a high-performance engineering team onsite in Santa Clara, CA. The ideal candidate will have strong expertise in SystemVerilog, UVM, and SoC-level verification with a proven track record in complex semiconductor environments.

Required Qualifications:
10+ years of Design Verification (DV) experience
Strong expertise in SystemVerilog
Strong expertise in UVM (Universal Verification Methodology)
Hands-on experience in SoC verification environments
Strong debugging and analytical problem-solving skills
Excellent communication and collaboration skills
Must be willing to work onsite in Santa Clara, CA

Preferred Qualifications:
System-level verification experience
Experience with AXI4 protocol
Scripting experience using Python, Perl, or Shell
C programming experience
Experience in verification infrastructure development, including:
Testbench development
VIP integration
Reusable verification components
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